{"id":244181,"date":"2024-10-19T16:02:14","date_gmt":"2024-10-19T16:02:14","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-61131-92013\/"},"modified":"2024-10-25T11:00:59","modified_gmt":"2024-10-25T11:00:59","slug":"bs-en-61131-92013","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-61131-92013\/","title":{"rendered":"BS EN 61131-9:2013"},"content":{"rendered":"

IEC 61131-9:2013 specifies a single-drop digital communication interface technology for small sensors and actuators SDCI (commonly known as IO-Link), which extends the traditional digital input and digital output interfaces as defined in IEC 61131-2 towards a point-to-point communication link. This technology enables the transfer of parameters to Devices and the delivery of diagnostic information from the Devices to the automation system.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
7<\/td>\nEnglish
CONTENTS <\/td>\n<\/tr>\n
19<\/td>\nINTRODUCTION <\/td>\n<\/tr>\n
21<\/td>\n1 Scope
2 Normative references <\/td>\n<\/tr>\n
22<\/td>\n3 Terms, definitions, symbols, abbreviated terms and conventions
3.1 Terms and definitions <\/td>\n<\/tr>\n
26<\/td>\n3.2 Symbols and abbreviated terms <\/td>\n<\/tr>\n
28<\/td>\n3.3 Conventions
3.3.1 General
3.3.2 Service parameters <\/td>\n<\/tr>\n
29<\/td>\n3.3.3 Service procedures
3.3.4 Service attributes
3.3.5 Figures
3.3.6 Transmission octet order
Figures
Figure\u00a01 \u2013 Example of a confirmed service <\/td>\n<\/tr>\n
30<\/td>\n3.3.7 Behavioral descriptions
4 Overview of SDCI (IO-LinkTM)
4.1 Purpose of technology
Figure\u00a02 \u2013 Memory storage and transmission order for WORD based data types
Figure\u00a03 \u2013 SDCI compatibility with IEC\u00a0611312 <\/td>\n<\/tr>\n
31<\/td>\n4.2 Positioning within the automation hierarchy
Figure\u00a04 \u2013 Domain of the SDCI technology within the automation hierarchy <\/td>\n<\/tr>\n
32<\/td>\n4.3 Wiring, connectors and power
4.4 Communication features of SDCI
Figure\u00a05 \u2013 Generic Device model for SDCI (Master’s view) <\/td>\n<\/tr>\n
33<\/td>\nFigure\u00a06 \u2013 Relationship between nature of data and transmission types <\/td>\n<\/tr>\n
34<\/td>\n4.5 Role of a Master
Figure\u00a07 \u2013 Object transfer at the application layer level (AL) <\/td>\n<\/tr>\n
35<\/td>\n4.6 SDCI configuration
4.7 Mapping to fieldbuses
4.8 Standard structure
Figure\u00a08 \u2013 Logical structure of Master and Device <\/td>\n<\/tr>\n
36<\/td>\n5 Physical Layer (PL)
5.1 General
5.1.1 Basics
5.1.2 Topology
Figure\u00a09 \u2013 Three wire connection system <\/td>\n<\/tr>\n
37<\/td>\n5.2 Physical layer services
5.2.1 Overview
Figure\u00a010 \u2013 Topology of SDCI
Figure\u00a011 \u2013 Physical layer (Master) <\/td>\n<\/tr>\n
38<\/td>\n5.2.2 PL services
Figure\u00a012 \u2013 Physical layer (Device)
Tables
Table\u00a01 \u2013 Service assignments of Master and Device
Table\u00a02 \u2013 PL_SetMode <\/td>\n<\/tr>\n
39<\/td>\nTable\u00a03 \u2013 PL_WakeUp
Table\u00a04 \u2013 PL_Transfer <\/td>\n<\/tr>\n
40<\/td>\n5.3 Transmitter\/Receiver
5.3.1 Description method
5.3.2 Electrical requirements
Figure\u00a013 \u2013 Line driver reference schematics
Figure\u00a014 \u2013 Receiver reference schematics <\/td>\n<\/tr>\n
41<\/td>\nFigure\u00a015 \u2013 Reference schematics for SDCI 3-wire connection system
Figure\u00a016 \u2013 Voltage level definitions <\/td>\n<\/tr>\n
42<\/td>\nFigure\u00a017 \u2013 Switching thresholds
Table\u00a05 \u2013 Electric characteristics of a receiver
Table\u00a06 \u2013 Electric characteristics of a Master port <\/td>\n<\/tr>\n
43<\/td>\nTable\u00a07 \u2013 Electric characteristics of a Device <\/td>\n<\/tr>\n
44<\/td>\n5.3.3 Timing requirements
Figure\u00a018 \u2013 Format of an SDCI UART frame <\/td>\n<\/tr>\n
45<\/td>\nFigure\u00a019 \u2013 Eye diagram for the ‘H’ and ‘L’ detection
Figure\u00a020 \u2013 Eye diagram for the correct detection of a UART frame <\/td>\n<\/tr>\n
46<\/td>\nTable\u00a08 \u2013 Dynamic characteristics of the transmission <\/td>\n<\/tr>\n
47<\/td>\n5.4 Power supply
5.4.1 Power supply options
Figure\u00a021 \u2013 Wake-up request
Table\u00a09 \u2013 Wake-up request characteristics <\/td>\n<\/tr>\n
48<\/td>\n5.4.2 Power-on requirements
5.5 Medium
5.5.1 Connectors
Figure\u00a022 \u2013 Power-on timing for Power1
Table\u00a010 \u2013 Power-on timing <\/td>\n<\/tr>\n
49<\/td>\nFigure\u00a023 \u2013 Pin layout front view
Table\u00a011 \u2013 Pin assignments <\/td>\n<\/tr>\n
50<\/td>\n5.5.2 Cable
Figure\u00a024 \u2013 Class A and B port definitions
Figure\u00a025 \u2013 Reference schematic for effective line capacitance and loop resistance
Table\u00a012 \u2013 Cable characteristics <\/td>\n<\/tr>\n
51<\/td>\n6 Standard Input and Output (SIO)
7 Data link layer (DL)
7.1 General
Table\u00a013 \u2013 Cable conductor assignments <\/td>\n<\/tr>\n
52<\/td>\nFigure\u00a026 \u2013 Structure and services of the data link layer (Master)
Figure\u00a027 \u2013 Structure and services of the data link layer (Device) <\/td>\n<\/tr>\n
53<\/td>\n7.2 Data link layer services
7.2.1 DL-B services
Table\u00a014 \u2013 Service assignments within Master and Device <\/td>\n<\/tr>\n
54<\/td>\nTable\u00a015 \u2013 DL_ReadParam
Table\u00a016 \u2013 DL_WriteParam <\/td>\n<\/tr>\n
55<\/td>\nTable\u00a017 \u2013 DL_Read <\/td>\n<\/tr>\n
56<\/td>\nTable\u00a018 \u2013 DL_Write <\/td>\n<\/tr>\n
57<\/td>\nTable\u00a019 \u2013 DL_ISDUTransport <\/td>\n<\/tr>\n
58<\/td>\nTable\u00a020 \u2013 DL_ISDUAbort
Table\u00a021 \u2013 DL_PDOutputUpdate <\/td>\n<\/tr>\n
59<\/td>\nTable\u00a022 \u2013 DL_PDOutputTransport <\/td>\n<\/tr>\n
60<\/td>\nTable\u00a023 \u2013 DL_PDInputUpdate
Table\u00a024 \u2013 DL_PDInputTransport <\/td>\n<\/tr>\n
61<\/td>\nTable\u00a025 \u2013 DL_PDCycle
Table\u00a026 \u2013 DL_SetMode <\/td>\n<\/tr>\n
62<\/td>\nTable\u00a027 \u2013 DL_Mode <\/td>\n<\/tr>\n
63<\/td>\nTable\u00a028 \u2013 DL_Event
Table\u00a029 \u2013 DL_EventConf <\/td>\n<\/tr>\n
64<\/td>\n7.2.2 DL-A services
Table\u00a030 \u2013 DL_EventTrigger
Table\u00a031 \u2013 DL_Control <\/td>\n<\/tr>\n
65<\/td>\nTable\u00a032 \u2013 DL-A services within Master and Device
Table\u00a033 \u2013 OD <\/td>\n<\/tr>\n
66<\/td>\nTable\u00a034 \u2013 PD <\/td>\n<\/tr>\n
67<\/td>\nTable\u00a035 \u2013 EventFlag <\/td>\n<\/tr>\n
68<\/td>\nTable\u00a036 \u2013 PDInStatus
Table\u00a037 \u2013 MHInfo <\/td>\n<\/tr>\n
69<\/td>\n7.3 Data link layer protocol
7.3.1 Overview
Table\u00a038 \u2013 ODTrig
Table\u00a039 \u2013 PDTrig <\/td>\n<\/tr>\n
70<\/td>\n7.3.2 DL-mode handler
Figure\u00a028 \u2013 State machines of the data link layer
Figure\u00a029 \u2013 Example of an attempt to establish communication <\/td>\n<\/tr>\n
71<\/td>\nFigure\u00a030 \u2013 Failed attempt to establish communication
Figure\u00a031 \u2013 Retry strategy to establish communication <\/td>\n<\/tr>\n
72<\/td>\nFigure\u00a032 \u2013 Fallback procedure
Table\u00a040 \u2013 Wake-up procedure and retry characteristics <\/td>\n<\/tr>\n
73<\/td>\nFigure\u00a033 \u2013 State machine of the Master DL-mode handler
Table\u00a041 \u2013 Fallback timing characteristics <\/td>\n<\/tr>\n
74<\/td>\nFigure\u00a034 \u2013 Submachine 1 to establish communication
Table\u00a042 \u2013 State transition tables of the Master DL-mode handler <\/td>\n<\/tr>\n
76<\/td>\nFigure\u00a035 \u2013 State machine of the Device DL-mode handler <\/td>\n<\/tr>\n
77<\/td>\nTable\u00a043 \u2013 State transition tables of the Device DL-mode handler <\/td>\n<\/tr>\n
78<\/td>\n7.3.3 Message handler
Figure\u00a036 \u2013 SDCI message sequences <\/td>\n<\/tr>\n
79<\/td>\nFigure\u00a037 \u2013 Overview of M-sequence types <\/td>\n<\/tr>\n
80<\/td>\nFigure\u00a038 \u2013 State machine of the Master message handler <\/td>\n<\/tr>\n
81<\/td>\nFigure\u00a039 \u2013 Submachine “Response 3” of the message handler
Figure\u00a040 \u2013 Submachine “Response 8” of the message handler
Figure\u00a041 \u2013 Submachine “Response 15” of the message handler <\/td>\n<\/tr>\n
82<\/td>\nTable\u00a044 \u2013 State transition table of the Master message handler <\/td>\n<\/tr>\n
84<\/td>\nFigure\u00a042 \u2013 State machine of the Device message handler <\/td>\n<\/tr>\n
85<\/td>\n7.3.4 Process Data handler
Table\u00a045 \u2013 State transition tables of the Device message handler <\/td>\n<\/tr>\n
86<\/td>\nFigure\u00a043 \u2013 Interleave mode for the segmented transmission of Process Data
Figure\u00a044 \u2013 State machine of the Master Process Data handler <\/td>\n<\/tr>\n
87<\/td>\nTable\u00a046 \u2013 State transition tables of the Master Process Data handler <\/td>\n<\/tr>\n
88<\/td>\n7.3.5 On-request Data handler
Figure\u00a045 \u2013 State machine of the Device Process Data handler
Table\u00a047 \u2013 State transition tables of the Device Process Data handler <\/td>\n<\/tr>\n
89<\/td>\nFigure\u00a046 \u2013 State machine of the Master On-request Data handler
Table\u00a048 \u2013 State transition tables of the Master On-request Data handler <\/td>\n<\/tr>\n
90<\/td>\nFigure\u00a047 \u2013 State machine of the Device On-request Data handler <\/td>\n<\/tr>\n
91<\/td>\n7.3.6 ISDU handler
Figure\u00a048 \u2013 Structure of the ISDU
Table\u00a049 \u2013 State transition tables of the Device On-request Data handler <\/td>\n<\/tr>\n
92<\/td>\nTable\u00a050 \u2013 FlowCTRL definitions <\/td>\n<\/tr>\n
93<\/td>\nFigure\u00a049 \u2013 State machine of the Master ISDU handler
Table\u00a051 \u2013 State transition tables of the Master ISDU handler <\/td>\n<\/tr>\n
94<\/td>\nFigure\u00a050 \u2013 State machine of the Device ISDU handler <\/td>\n<\/tr>\n
95<\/td>\n7.3.7 Command handler
Table\u00a052 \u2013 State transition tables of the Device ISDU handler <\/td>\n<\/tr>\n
96<\/td>\nFigure\u00a051 \u2013 State machine of the Master command handler
Table\u00a053 \u2013 Control codes
Table\u00a054 \u2013 State transition tables of the Master command handler <\/td>\n<\/tr>\n
97<\/td>\nFigure\u00a052 \u2013 State machine of the Device command handler
Table\u00a055 \u2013 State transition tables of the Device command handler <\/td>\n<\/tr>\n
98<\/td>\n7.3.8 Event handler
Table\u00a056 \u2013 Event memory <\/td>\n<\/tr>\n
99<\/td>\nFigure\u00a053 \u2013 State machine of the Master Event handler
Table\u00a057 \u2013 State transition tables of the Master Event handler <\/td>\n<\/tr>\n
100<\/td>\nFigure\u00a054 \u2013 State machine of the Device Event handler
Table\u00a058 \u2013 State transition tables of the Device Event handler <\/td>\n<\/tr>\n
101<\/td>\n8 Application layer (AL)
8.1 General
Figure\u00a055 \u2013 Structure and services of the application layer (Master) <\/td>\n<\/tr>\n
102<\/td>\n8.2 Application layer services
8.2.1 AL services within Master and Device
Figure\u00a056 \u2013 Structure and services of the application layer (Device)
Table\u00a059 \u2013 AL services within Master and Device <\/td>\n<\/tr>\n
103<\/td>\n8.2.2 AL Services
Table\u00a060 \u2013 AL_Read <\/td>\n<\/tr>\n
104<\/td>\nTable\u00a061 \u2013 AL_Write <\/td>\n<\/tr>\n
105<\/td>\nTable\u00a062 \u2013 AL_Abort
Table\u00a063 \u2013 AL_GetInput <\/td>\n<\/tr>\n
106<\/td>\nTable\u00a064 \u2013 AL_NewInput <\/td>\n<\/tr>\n
107<\/td>\nTable\u00a065 \u2013 AL_SetInput
Table\u00a066 \u2013 AL_PDCycle <\/td>\n<\/tr>\n
108<\/td>\nTable\u00a067 \u2013 AL_GetOutput
Table\u00a068 \u2013 AL_NewOutput <\/td>\n<\/tr>\n
109<\/td>\nTable\u00a069 \u2013 AL_SetOutput <\/td>\n<\/tr>\n
110<\/td>\nTable\u00a070 \u2013 AL_Event <\/td>\n<\/tr>\n
111<\/td>\n8.3 Application layer protocol
8.3.1 Overview
8.3.2 On-request Data transfer
Table\u00a071 \u2013 AL_Control <\/td>\n<\/tr>\n
112<\/td>\nFigure\u00a057 \u2013 OD state machine of the Master AL
Table\u00a072 \u2013 States and transitions for the OD state machine of the Master AL <\/td>\n<\/tr>\n
113<\/td>\nFigure\u00a058 \u2013 OD state machine of the Device AL <\/td>\n<\/tr>\n
114<\/td>\nTable\u00a073 \u2013 States and transitions for the OD state machine of the Device AL <\/td>\n<\/tr>\n
115<\/td>\nFigure\u00a059 \u2013 Sequence diagram for the transmission of On-request Data <\/td>\n<\/tr>\n
116<\/td>\nFigure\u00a060 \u2013 Sequence diagram for On-request Data in case of errors
Figure\u00a061 \u2013 Sequence diagram for On-request Data in case of timeout <\/td>\n<\/tr>\n
117<\/td>\n8.3.3 Event processing
Figure\u00a062 \u2013 Event state machine of the Master AL
Table\u00a074 \u2013 State and transitions of the Event state machine of the Master AL <\/td>\n<\/tr>\n
118<\/td>\nFigure\u00a063 \u2013 Event state machine of the Device AL
Table\u00a075 \u2013 State and transitions of the Event state machine of the Device AL <\/td>\n<\/tr>\n
119<\/td>\nFigure\u00a064 \u2013 Single Event scheduling <\/td>\n<\/tr>\n
120<\/td>\n8.3.4 Process Data cycles
Figure\u00a065 \u2013 Sequence diagram for output Process Data <\/td>\n<\/tr>\n
121<\/td>\n9 System management (SM)
9.1 General
9.2 System management of the Master
9.2.1 Overview
Figure\u00a066 \u2013 Sequence diagram for input Process Data <\/td>\n<\/tr>\n
122<\/td>\nFigure\u00a067 \u2013 Structure and services of the Master system management <\/td>\n<\/tr>\n
123<\/td>\n9.2.2 SM Master services
Figure\u00a068 \u2013 Sequence chart of the use case “port x setup” <\/td>\n<\/tr>\n
124<\/td>\nTable\u00a076 \u2013 SM services within the Master
Table\u00a077 \u2013 SM_SetPortConfig <\/td>\n<\/tr>\n
125<\/td>\nTable\u00a078 \u2013 Definition of the InspectionLevel (IL) <\/td>\n<\/tr>\n
126<\/td>\nTable\u00a079 \u2013 Definitions of the Target Modes
Table\u00a080 \u2013 SM_GetPortConfig <\/td>\n<\/tr>\n
127<\/td>\nTable\u00a081 \u2013 SM_PortMode <\/td>\n<\/tr>\n
128<\/td>\n9.2.3 SM Master protocol
Table\u00a082 \u2013 SM_Operate <\/td>\n<\/tr>\n
129<\/td>\nFigure\u00a069 \u2013 Main state machine of the Master system management <\/td>\n<\/tr>\n
130<\/td>\nTable\u00a083 \u2013 State transition tables of the Master system management <\/td>\n<\/tr>\n
131<\/td>\nFigure\u00a070 \u2013 SM Master submachine CheckCompatibility_1
Table\u00a084 \u2013 State transition tables of the Master submachine CheckCompatibility_1 <\/td>\n<\/tr>\n
133<\/td>\nFigure\u00a071 \u2013 Activity for state “CheckVxy”
Figure\u00a072 \u2013 Activity for state “CheckCompV10” <\/td>\n<\/tr>\n
134<\/td>\nFigure\u00a073 \u2013 Activity for state “CheckComp”
Figure\u00a074 \u2013 Activity (write parameter) in state “RestartDevice” <\/td>\n<\/tr>\n
135<\/td>\nFigure\u00a075 \u2013 SM Master submachine CheckSerNum_3
Table\u00a085 \u2013 State transition tables of the Master submachine CheckSerNum_3 <\/td>\n<\/tr>\n
136<\/td>\n9.3 System management of the Device
9.3.1 Overview
Figure\u00a076 \u2013 Activity (check SerialNumber) for state CheckSerNum_3 <\/td>\n<\/tr>\n
137<\/td>\nFigure\u00a077 \u2013 Structure and services of the system management (Device) <\/td>\n<\/tr>\n
138<\/td>\n9.3.2 SM Device services
Figure\u00a078 \u2013 Sequence chart of the use case “INACTIVE \u2013 SIO \u2013 SDCI \u2013 SIO” <\/td>\n<\/tr>\n
139<\/td>\nTable\u00a086 \u2013 SM services within the Device
Table\u00a087 \u2013 SM_SetDeviceCom <\/td>\n<\/tr>\n
140<\/td>\nTable\u00a088 \u2013 SM_GetDeviceCom <\/td>\n<\/tr>\n
141<\/td>\nTable\u00a089 \u2013 SM_SetDeviceIdent <\/td>\n<\/tr>\n
142<\/td>\nTable\u00a090 \u2013 SM_GetDeviceIdent <\/td>\n<\/tr>\n
143<\/td>\nTable\u00a091 \u2013 SM_SetDeviceMode <\/td>\n<\/tr>\n
144<\/td>\n9.3.3 SM Device protocol
Table\u00a092 \u2013 SM_DeviceMode <\/td>\n<\/tr>\n
145<\/td>\nFigure\u00a079 \u2013 State machine of the Device system management
Table\u00a093 \u2013 State transition tables of the Device system management <\/td>\n<\/tr>\n
148<\/td>\nFigure\u00a080 \u2013 Sequence chart of a regular Device startup <\/td>\n<\/tr>\n
149<\/td>\nFigure\u00a081 \u2013 Sequence chart of a Device startup in compatibility mode <\/td>\n<\/tr>\n
150<\/td>\nFigure\u00a082 \u2013 Sequence chart of a Device startup when compatibility fails <\/td>\n<\/tr>\n
151<\/td>\n10 Device
10.1 Overview
Figure\u00a083 \u2013 Structure and services of a Device <\/td>\n<\/tr>\n
152<\/td>\n10.2 Process Data Exchange (PDE)
10.3 Parameter Manager (PM)
10.3.1 General
10.3.2 Parameter manager state machine <\/td>\n<\/tr>\n
153<\/td>\nFigure\u00a084 \u2013 The Parameter Manager (PM) state machine
Table\u00a094 \u2013 State transition tables of the PM state machine <\/td>\n<\/tr>\n
154<\/td>\n10.3.3 Dynamic parameter <\/td>\n<\/tr>\n
155<\/td>\n10.3.4 Single parameter
Figure\u00a085 \u2013 Positive and negative parameter checking result
Table\u00a095 \u2013 Definitions of parameter checks <\/td>\n<\/tr>\n
156<\/td>\n10.3.5 Block parameter
Figure\u00a086 \u2013 Positive block parameter download with Data Storage request <\/td>\n<\/tr>\n
157<\/td>\nFigure\u00a087 \u2013 Negative block parameter download <\/td>\n<\/tr>\n
158<\/td>\n10.3.6 Concurrent parameterization access
10.3.7 Command handling
10.4 Data Storage (DS)
10.4.1 General
10.4.2 Data Storage state machine <\/td>\n<\/tr>\n
159<\/td>\nFigure\u00a088 \u2013 The Data Storage (DS) state machine
Table\u00a096 \u2013 State transition table of the Data Storage state machine <\/td>\n<\/tr>\n
160<\/td>\n10.4.3 DS configuration
10.4.4 DS memory space
Figure\u00a089 \u2013 Data Storage request message sequence <\/td>\n<\/tr>\n
161<\/td>\n10.4.5 DS Index_List
10.4.6 DS parameter availability
10.4.7 DS without ISDU
10.4.8 DS parameter change indication
10.5 Event Dispatcher (ED)
10.6 Device features
10.6.1 General <\/td>\n<\/tr>\n
162<\/td>\n10.6.2 Device backward compatibility
10.6.3 Protocol revision compatibility
10.6.4 Factory settings
10.6.5 Application reset
10.6.6 Device reset
10.6.7 Visual SDCI indication <\/td>\n<\/tr>\n
163<\/td>\n10.6.8 Parameter access locking
10.6.9 Data Storage locking
10.6.10 Device parameter locking
10.6.11 Device user interface locking
10.6.12 Offset time
Figure\u00a090 \u2013 Cycle timing <\/td>\n<\/tr>\n
164<\/td>\n10.6.13 Data Storage concept
10.6.14 Block Parameter
10.7 Device design rules and constraints
10.7.1 General
10.7.2 Process Data
10.7.3 Communication loss
10.7.4 Direct Parameter <\/td>\n<\/tr>\n
165<\/td>\n10.7.5 ISDU communication channel
10.7.6 DeviceID rules related to Device variants
10.7.7 Protocol constants
Table\u00a097 \u2013 Overview of the protocol constants for Devices <\/td>\n<\/tr>\n
166<\/td>\n10.8 IO Device description (IODD)
10.9 Device diagnosis
10.9.1 Concepts <\/td>\n<\/tr>\n
167<\/td>\n10.9.2 Events
Table\u00a098 \u2013 Classification of Device diagnosis incidents <\/td>\n<\/tr>\n
168<\/td>\n10.9.3 Visual indicators
Figure\u00a091 \u2013 Event flow in case of successive errors
Figure\u00a092 \u2013 Device LED indicator timing
Table\u00a099 \u2013 Timing for LED indicators <\/td>\n<\/tr>\n
169<\/td>\n10.10 Device connectivity
11 Master
11.1 Overview
11.1.1 Generic model for the system integration of a Master
11.1.2 Structure and services of a Master
Figure\u00a093 \u2013 Generic relationship of SDCI technology and fieldbus technology <\/td>\n<\/tr>\n
171<\/td>\nFigure\u00a094 \u2013 Structure and services of a Master
Figure\u00a095 \u2013 Relationship of the common Master applications <\/td>\n<\/tr>\n
172<\/td>\n11.2 Configuration Manager (CM)
11.2.1 General
Table\u00a0100 \u2013 Internal variables and Events to control the common Master applications <\/td>\n<\/tr>\n
173<\/td>\nFigure\u00a096 \u2013 Sequence diagram of configuration manager actions <\/td>\n<\/tr>\n
174<\/td>\n11.2.2 Configuration parameter
Figure\u00a097 \u2013 Ports in MessageSync mode <\/td>\n<\/tr>\n
176<\/td>\n11.2.3 State machine of the Configuration Manager
Figure\u00a098 \u2013 State machine of the Configuration Manager <\/td>\n<\/tr>\n
177<\/td>\nTable\u00a0101 \u2013 State transition tables of the Configuration Manager <\/td>\n<\/tr>\n
178<\/td>\n11.3 Data Storage (DS)
11.3.1 Overview
11.3.2 DS data object
11.3.3 DS state machine
Figure\u00a099 \u2013 Main state machine of the Data Storage mechanism <\/td>\n<\/tr>\n
179<\/td>\nFigure\u00a0100 \u2013 Submachine “UpDownload_2” of the Data Storage mechanism <\/td>\n<\/tr>\n
180<\/td>\nFigure\u00a0101 \u2013 Data Storage submachine “Upload_7”
Figure\u00a0102 \u2013 Data Storage upload sequence diagram <\/td>\n<\/tr>\n
181<\/td>\nFigure\u00a0103 \u2013 Data Storage submachine “Download_10”
Figure\u00a0104 \u2013 Data Storage download sequence diagram <\/td>\n<\/tr>\n
182<\/td>\nTable\u00a0102 \u2013 States and transitions of the Data Storage state machines <\/td>\n<\/tr>\n
184<\/td>\n11.3.4 Parameter selection for Data Storage
11.4 On-Request Data exchange (ODE)
Figure\u00a0105 \u2013 State machine of the On-request Data Exchange
Table\u00a0103 \u2013 State transition table of the ODE state machine <\/td>\n<\/tr>\n
185<\/td>\n11.5 Diagnosis Unit (DU) <\/td>\n<\/tr>\n
186<\/td>\n11.6 PD Exchange (PDE)
11.6.1 General
11.6.2 Process Data mapping
Figure\u00a0106 \u2013 System overview of SDCI diagnosis information propagation via Events <\/td>\n<\/tr>\n
187<\/td>\n11.6.3 Process Data invalid\/valid qualifier status
Figure\u00a0107 \u2013 Process Data mapping from ports to the gateway data stream
Figure\u00a0108 \u2013 Propagation of PD qualifier status between Master and Device <\/td>\n<\/tr>\n
188<\/td>\n11.7 Port and Device configuration tool (PDCT)
11.7.1 General
11.7.2 Basic layout examples
Figure\u00a0109 \u2013 Example 1 of a PDCT display layout <\/td>\n<\/tr>\n
189<\/td>\n11.8 Gateway application
11.8.1 General
11.8.2 Changing Device configuration including Data Storage
11.8.3 Parameter server and recipe control
11.8.4 Anonymous parameters
Figure\u00a0110 \u2013 Example 2 of a PDCT display layout <\/td>\n<\/tr>\n
190<\/td>\n11.8.5 Virtual port mode DIwithSDCI
Figure\u00a0111 \u2013 Alternative Device configuration <\/td>\n<\/tr>\n
191<\/td>\nFigure\u00a0112 \u2013 Virtual port mode “DIwithSDCI”
Table\u00a0104 \u2013 State transitions of the state machine “DIwithSDCI” <\/td>\n<\/tr>\n
193<\/td>\nAnnex A (normative) Codings, timing constraints, and errors
Figure\u00a0A.1 \u2013 M-sequence control
Table\u00a0A.1 \u2013 Values of communication channel <\/td>\n<\/tr>\n
194<\/td>\nFigure\u00a0A.2 \u2013 Checksum\/M-sequence type octet
Table\u00a0A.2 \u2013 Values of R\/W
Table\u00a0A.3 \u2013 Values of M-sequence types <\/td>\n<\/tr>\n
195<\/td>\nFigure\u00a0A.3 \u2013 Checksum\/status octet
Table\u00a0A.4 \u2013 Data types for user data
Table\u00a0A.5 \u2013 Values of PD status <\/td>\n<\/tr>\n
196<\/td>\nFigure\u00a0A.4 \u2013 Principle of the checksum calculation and compression
Table\u00a0A.6 \u2013 Values of the Event flag <\/td>\n<\/tr>\n
197<\/td>\nFigure\u00a0A.5 \u2013 M-sequence TYPE_0
Figure\u00a0A.6 \u2013 M-sequence TYPE_1_1 <\/td>\n<\/tr>\n
198<\/td>\nFigure\u00a0A.7 \u2013 M-sequence TYPE_1_2
Figure\u00a0A.8 \u2013 M-sequence TYPE_1_V <\/td>\n<\/tr>\n
199<\/td>\nFigure\u00a0A.9 \u2013 M-sequence TYPE_2_1
Figure\u00a0A.10 \u2013 M-sequence TYPE_2_2
Figure\u00a0A.11 \u2013 M-sequence TYPE_2_3 <\/td>\n<\/tr>\n
200<\/td>\nFigure\u00a0A.12 \u2013 M-sequence TYPE_2_4
Figure\u00a0A.13 \u2013 M-sequence TYPE_2_5
Figure\u00a0A.14 \u2013 M-sequence TYPE_2_6 <\/td>\n<\/tr>\n
201<\/td>\nFigure\u00a0A.15 \u2013 M-sequence TYPE_2_V
Table\u00a0A.7 \u2013 M-sequence types for the STARTUP mode
Table\u00a0A.8 \u2013 M-sequence types for the PREOPERATE mode <\/td>\n<\/tr>\n
202<\/td>\nTable\u00a0A.9 \u2013 M-sequence types for the OPERATE mode (legacy protocol)
Table\u00a0A.10 \u2013 M-sequence types for the OPERATE mode <\/td>\n<\/tr>\n
204<\/td>\nFigure\u00a0A.16 \u2013 M-sequence timing
Table\u00a0A.11 \u2013 Recommended MinCycleTimes <\/td>\n<\/tr>\n
206<\/td>\nFigure\u00a0A.17 \u2013 I-Service octet
Table\u00a0A.12 \u2013 Definition of the nibble “I-Service” <\/td>\n<\/tr>\n
207<\/td>\nTable\u00a0A.13 \u2013 ISDU syntax
Table\u00a0A.14 \u2013 Definition of nibble Length and octet ExtLength <\/td>\n<\/tr>\n
208<\/td>\nFigure\u00a0A.18 \u2013 Check of ISDU integrity via CHKPDU
Table\u00a0A.15 \u2013 Use of Index formats <\/td>\n<\/tr>\n
209<\/td>\nFigure\u00a0A.19 \u2013 Examples of request formats for ISDUs
Figure\u00a0A.20 \u2013 Examples of response ISDUs <\/td>\n<\/tr>\n
210<\/td>\nFigure\u00a0A.21 \u2013 Examples of read and write request ISDUs <\/td>\n<\/tr>\n
211<\/td>\nFigure\u00a0A.22 \u2013 Structure of StatusCode type 1
Figure\u00a0A.23 \u2013 Structure of StatusCode type 2
Table\u00a0A.16 \u2013 Mapping of EventCodes (type 1) <\/td>\n<\/tr>\n
212<\/td>\nFigure\u00a0A.24 \u2013 Indication of activated Events
Figure\u00a0A.25 \u2013 Structure of the EventQualifier
Table\u00a0A.17 \u2013 Values of INSTANCE <\/td>\n<\/tr>\n
213<\/td>\nTable\u00a0A.18 \u2013 Values of SOURCE
Table\u00a0A.19 \u2013 Values of TYPE
Table\u00a0A.20 \u2013 Values of MODE <\/td>\n<\/tr>\n
214<\/td>\nAnnex B (normative) Parameter and commands
Figure\u00a0B.1 \u2013 Classification and mapping of Direct Parameters <\/td>\n<\/tr>\n
215<\/td>\nTable\u00a0B.1 \u2013 Direct Parameter page 1 and 2 <\/td>\n<\/tr>\n
216<\/td>\nFigure\u00a0B.2 \u2013 MinCycleTime
Table\u00a0B.2 \u2013 Types of MasterCommands <\/td>\n<\/tr>\n
217<\/td>\nFigure\u00a0B.3 \u2013 M-sequence Capability
Table\u00a0B.3 \u2013 Possible values of MasterCycleTime and MinCycleTime
Table\u00a0B.4 \u2013 Values of ISDU <\/td>\n<\/tr>\n
218<\/td>\nFigure\u00a0B.4 \u2013 RevisionID
Figure\u00a0B.5 \u2013 ProcessDataIn
Table\u00a0B.5 \u2013 Values of SIO
Table\u00a0B.6 \u2013 Permitted combinations of BYTE and Length <\/td>\n<\/tr>\n
220<\/td>\nFigure\u00a0B.6 \u2013 Index space for ISDU data objects
Table\u00a0B.7 \u2013 Implementation rules for parameters and commands <\/td>\n<\/tr>\n
221<\/td>\nTable\u00a0B.8 \u2013 Index assignment of data objects (Device parameter) <\/td>\n<\/tr>\n
222<\/td>\nTable\u00a0B.9 \u2013 Coding of SystemCommand (ISDU) <\/td>\n<\/tr>\n
223<\/td>\nTable\u00a0B.10 \u2013 Data Storage Index assignments <\/td>\n<\/tr>\n
224<\/td>\nTable\u00a0B.11 \u2013 Structure of Index_List <\/td>\n<\/tr>\n
225<\/td>\nTable\u00a0B.12 \u2013 Device locking possibilities <\/td>\n<\/tr>\n
227<\/td>\nTable\u00a0B.13 \u2013 Device status parameter <\/td>\n<\/tr>\n
228<\/td>\nTable\u00a0B.14 \u2013 Detailed Device Status (Index 0x0025) <\/td>\n<\/tr>\n
229<\/td>\nFigure\u00a0B.7 \u2013 Structure of the Offset Time
Table\u00a0B.15 \u2013 Time base coding and values of Offset Time <\/td>\n<\/tr>\n
231<\/td>\nAnnex C (normative) ErrorTypes (ISDU errors)
Table\u00a0C.1 \u2013 ErrorTypes <\/td>\n<\/tr>\n
234<\/td>\nTable\u00a0C.2 \u2013 Derived ErrorTypes <\/td>\n<\/tr>\n
236<\/td>\nAnnex D (normative) EventCodes (diagnosis information)
Table\u00a0D.1 \u2013 EventCodes <\/td>\n<\/tr>\n
238<\/td>\nTable\u00a0D.2 \u2013 Basic SDCI EventCodes <\/td>\n<\/tr>\n
239<\/td>\nAnnex E (normative) Data types
Table\u00a0E.1 \u2013 BooleanT
Table\u00a0E.2 \u2013 BooleanT coding <\/td>\n<\/tr>\n
240<\/td>\nFigure\u00a0E.1 \u2013 Coding examples of UIntegerT
Table\u00a0E.3 \u2013 UIntegerT
Table\u00a0E.4 \u2013 IntegerT <\/td>\n<\/tr>\n
241<\/td>\nTable\u00a0E.5 \u2013 IntegerT coding (8 octets)
Table\u00a0E.6 \u2013 IntegerT coding (4 octets)
Table\u00a0E.7 \u2013 IntegerT coding (2 octets)
Table\u00a0E.8 \u2013 IntegerT coding (1 octet) <\/td>\n<\/tr>\n
242<\/td>\nFigure\u00a0E.2 \u2013 Coding examples of IntegerT
Table\u00a0E.9 \u2013 Float32T
Table\u00a0E.10 \u2013 Coding of Float32T <\/td>\n<\/tr>\n
243<\/td>\nFigure\u00a0E.3 \u2013 Singular access of StringT
Table\u00a0E.11 \u2013 StringT
Table\u00a0E.12 \u2013 OctetStringT <\/td>\n<\/tr>\n
244<\/td>\nFigure\u00a0E.4 \u2013 Coding example of OctetStringT
Figure\u00a0E.5 \u2013 Definition of TimeT
Table\u00a0E.13 \u2013 TimeT <\/td>\n<\/tr>\n
245<\/td>\nTable\u00a0E.14 \u2013 Coding of TimeT
Table\u00a0E.15 \u2013 TimeSpanT
Table\u00a0E.16 \u2013 Coding of TimeSpanT <\/td>\n<\/tr>\n
246<\/td>\nFigure\u00a0E.6 \u2013 Example of an ArrayT data structure
Table\u00a0E.17 \u2013 Structuring rules for ArrayT
Table\u00a0E.18 \u2013 Example for the access of an ArrayT <\/td>\n<\/tr>\n
247<\/td>\nTable\u00a0E.19 \u2013 Structuring rules for RecordT
Table\u00a0E.20 \u2013 Example 1 for the access of a RecordT
Table\u00a0E.21 \u2013 Example 2 for the access of a RecordT <\/td>\n<\/tr>\n
248<\/td>\nFigure\u00a0E.7 \u2013 Example 2 of a RecordT structure
Figure\u00a0E.8 \u2013 Example 3 of a RecordT structure
Table\u00a0E.22 \u2013 Example 3 for the access of a RecordT <\/td>\n<\/tr>\n
249<\/td>\nFigure\u00a0E.9 \u2013 Write requests for example 3 <\/td>\n<\/tr>\n
250<\/td>\nAnnex F (normative) Structure of the Data Storage data object
Table\u00a0F.1 \u2013 Structure of the stored DS data object
Table\u00a0F.2 \u2013 Associated header information for stored DS data objects <\/td>\n<\/tr>\n
251<\/td>\nAnnex G (normative) Master and Device conformity
Table\u00a0G.1 \u2013 EMC test conditions for SDCI <\/td>\n<\/tr>\n
252<\/td>\nTable\u00a0G.2 \u2013 EMC test levels <\/td>\n<\/tr>\n
253<\/td>\nFigure\u00a0G.1 \u2013 Test setup for electrostatic discharge (Master)
Figure\u00a0G.2 \u2013 Test setup for RF electromagnetic field (Master) <\/td>\n<\/tr>\n
254<\/td>\nFigure\u00a0G.3 \u2013 Test setup for fast transients (Master)
Figure\u00a0G.4 \u2013 Test setup for RF common mode (Master) <\/td>\n<\/tr>\n
255<\/td>\nFigure\u00a0G.5 \u2013 Test setup for electrostatic discharges (Device)
Figure\u00a0G.6 \u2013 Test setup for RF electromagnetic field (Device)
Figure\u00a0G.7 \u2013 Test setup for fast transients (Device) <\/td>\n<\/tr>\n
256<\/td>\nFigure\u00a0G.8 \u2013 Test setup for RF common mode (Device) <\/td>\n<\/tr>\n
257<\/td>\nAnnex H (informative) Residual error probabilities
Figure\u00a0H.1 \u2013 Residual error probability for the SDCI data integrity mechanism <\/td>\n<\/tr>\n
259<\/td>\nAnnex I (informative) Example sequence of an ISDU transmission
Figure\u00a0I.1 \u2013 Example for ISDU transmissions (1 of 2) <\/td>\n<\/tr>\n
261<\/td>\nAnnex J (informative) Recommended methods for detecting parameter changes
Table\u00a0J.1 \u2013 Proper CRC generator polynomials <\/td>\n<\/tr>\n
262<\/td>\nBibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Programmable controllers – Single-drop digital communication interface for small sensors and actuators (SDCI)<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
BSI<\/b><\/a><\/td>\n2014<\/td>\n264<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":244182,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[385,2641],"product_tag":[],"class_list":{"0":"post-244181","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-25-040-40","7":"product_cat-bsi","9":"first","10":"instock","11":"sold-individually","12":"shipping-taxable","13":"purchasable","14":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/244181","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/244182"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=244181"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=244181"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=244181"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}