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IEEE 1212 2002

$58.50

IEEE Standard for a Control and Status Registers (CSR) Architecture for Microcomputer Buses

Published By Publication Date Number of Pages
IEEE 2002 74
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Revision Standard – Inactive – Withdrawn. Administratively withdrawn January 2007 A common bus architecture (which includes functional components–modules, nodes,and units–and their address space, transaction set, CSRs, and configuration information) suitablefor both parallel and serial buses is provided in this standard. Bus bridges are enabled by the archi-tecture, but their details are beyond its scope. Configuration information is self- administered byvendors and organizations based upon IEEE Registration Authority company_id.

PDF Catalog

PDF Pages PDF Title
1 Cover Page
2 Title Page
4 Introduction
5 Participants
7 CONTENTS
8 1. Overview
1.1 Scope
9 1.2 Purpose
2. References
10 3. Definitions and notation
3.1 Definitions
13 3.2 Notation
14 4. Architectural framework
4.1 Modules, nodes, and units
15 4.2 Addressing
17 5. Transaction set
5.1 Read and write transactions
18 5.2 Lock transactions
20 5.3 Bus-dependent transactions
5.4 Split transactions
21 5.5 Completion status
6. CSR definitions
24 6.1 STATE_CLEAR / STATE_SET registers
6.2 NODE_IDS register
25 6.3 RESET_START register
26 6.4 SPLIT_TIMEOUT register
27 6.5 MESSAGE_REQUEST / MESSAGE_RESPONSE registers
28 7. Configuration ROM
29 7.1 IEEE Registration Authority
7.2 ROM formats
34 7.3 CRC calculation
35 7.4 Minimal ASCII
36 7.5 Data structures
51 7.6 Required and optional usage
56 7.7 Directory entries
67 Annex A (informative) Configuration ROM examples
73 Annex B (informative) Keyword examples
74 Annex C (information) Bibliography
IEEE 1212 2002
$58.50