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BS EN IEC 63373:2022

BS EN IEC 63373:2022

$102.76

Dynamic on-resistance test method guidelines for GaN HEMT based power conversion devices

Published By Publication Date Number of Pages
BSI 2022 20
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In general, dynamic ON-resistance testing is a measure of charge trapping phenomena in GaN power transistors. This publication describes the guidelines for testing dynamic ON-resistance of GaN lateral power transistor solutions. The test methods can be applied to the following: a) GaN enhancement and depletion-mode discrete power devices [1] b) GaN integrated power solutions c) the above in wafer and package levels Wafer level tests are recommended to minimize parasitic effects when performing high precision measurements. For package level tests, the impact of package thermal characteristics should be considered so as to minimize any device under test (DUT) self-heating implications. The prescribed test methods may be used for device characterization, production testing, reliability evaluations and application assessments of GaN power conversion devices. This document is not intended to cover the underlying mechanisms of dynamic ON-resistance and its symbolic representation for product specifications.

PDF Catalog

PDF Pages PDF Title
2 undefined
4 European foreword
Endorsement notice
6 English
CONTENTS
7 FOREWORD
9 INTRODUCTION
10 1 Scope
2 Normative references
3 Terms, definitions, symbols and abbreviated terms
3.1 Terms and definitions
3.2 Symbols and abbreviated terms
11 4 Test circuits and waveforms
4.1 General
4.2 Inductive and resistive switching methods
12 Figures
Figure 1 ā€“ Inductive-resistive load ā€œdouble-pulseā€ test circuit for hard-switching evaluation
Figure 2 ā€“ Depiction of the hard-switching ā€œdouble-pulseā€ test circuit (showing its similarity to a boost converter)
13 Figure 3 ā€“ Simplified flowchart for inductive and/or resistive switching based dynamic on-resistance test
14 4.3 Pulsed current-voltage (I-V) method
Figure 4 ā€“ Representative continuous-pulse hard-switching waveforms for measuring dynamic on-resistance using the test circuits in Figure 1 and Figure 2
Figure 5 ā€“ Example test circuit for soft-switching on-resistance measurement(the gate and drain terminals are pulsed with independent voltage signals)
15 Figure 6 ā€“ Simplified flowchart for soft switching based dynamic on-resistance test
16 5 Requirements
Figure 7 ā€“ Illustrative timing diagram for measuring dynamic ON-resistance under OFF-state stress in soft-switching mode
18 Bibliography

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BS EN IEC 63373:2022
$102.76