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BS EN 62680-3-1:2017

BS EN 62680-3-1:2017

$215.11

Universal Serial Bus interfaces for data and power – Universal Serial Bus 3.1 Specification (IEC 62680-3-1:2017)

Published By Publication Date Number of Pages
BSI 2017 644
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The specification is primarily targeted at peripheral developers and platform/adapter developers, but provides valuable information for platform operating system/BIOS/device driver, adapter IHVs/ISVs, and system OEMs. This specification can be used for developing new products and associated software.

Product developers using this specification are expected to know and understand the USB 2.0 Specification. Specifically, USB 3.1 devices must implement device framework commands and descriptors as defined in the USB 2.0 Specification. Devices operating at the new 10 Gbps (Gen 2) speed must implement the SuperSpeedPlus enhancements defined in this version of the specification.

PDF Catalog

PDF Pages PDF Title
2 undefined
5 FOREWORD
7 INTRODUCTION
18 CONTENTS
41 1 Introduction
1.1 Background
1.2 Objective of the Specification
1.3 Scope of the Document
42 1.4 USB Product Compliance
1.5 Document Organization
1.6 Design Goals
1.7 Related Documents
43 2 Terms and Abbreviations
51 3 Architectural Overview
Figures
Figure 2-1 – Port and Link Pictorial
52 3.1 USB 3.1 System Description
Figure 3-1 – USB 3.1 Dual Bus System Architecture
53 3.1.1 USB 3.1 Physical Interface
3.1.2 USB 3.1 Power
Figure 3-2 – USB 3.1 Cable
54 3.1.3 USB 3.1 System Configuration
3.1.4 USB 3.1 Architecture Summary
3.2 Enhanced SuperSpeed Bus Architecture
Tables
Table 3-1 – Comparing Enhanced SuperSpeed Bus to USB 2.0 Bus
55 Figure 3-3 – USB 3.1 Terminology Reference Model
56 3.2.1 Physical Layer
Figure 3-4 – Enhanced SuperSpeed Bus Communications Layers andPower Management Elements
57 3.2.2 Link Layer
58 3.2.3 Protocol Layer
60 3.2.4 Robustness
3.2.5 Enhanced SuperSpeed Power Management
61 3.2.6 Devices
62 Figure 3-5 – Examples of Supported USB 3.1 USB Physical Device Topologies
63 Figure 3-6 – SuperSpeed Only Enhanced SuperSpeed Peripheral Device Configuration
Figure 3-7 – Enhanced SuperSpeed Device Configuration
65 3.2.7 Hosts
Figure 3-8 – Multiple SuperSpeed Bus Instances in an Enhanced SuperSpeed System
66 3.3 Enhanced SuperSpeed Bus Data Flow Models
4 Enhanced SuperSpeed Data Flow Model
4.1 Implementer Viewpoints
67 4.2 Enhanced SuperSpeed Communication Flow
4.2.1 Pipes
4.3 Enhanced SuperSpeed Protocol Overview
4.3.1 Differences from USB 2.0
69 4.4 Generalized Transfer Description
70 4.4.1 Data Bursting
4.4.2 IN Transfers
71 4.4.3 OUT Transfers
Figure 4-1 – Enhanced SuperSpeed IN Transaction Protocol
72 4.4.4 Power Management and Performance
4.4.5 Control Transfers
Figure 4-2 – Enhanced SuperSpeed OUT Transaction Protocol
74 4.4.6 Bulk Transfers
75 Figure 4-3 – Enhanced SuperSpeed IN Stream Example
77 4.4.7 Interrupt Transfers
78 4.4.8 Isochronous Transfers
82 4.4.9 Device Notifications
4.4.10 Reliability
4.4.11 Efficiency
83 5 Mechanical
5.1 Objective
5.2 Significant Features
5.2.1 Connectors
84 Table 5-1 – Plugs Accepted By Receptacles
85 5.2.2 Allowed Cable Assemblies
5.2.3 Raw Cables
5.3 Connector Mating Interfaces
5.3.1 USB 3.1 Standard-A Connector
88 Figure 5-1 – USB 3.1 Standard-A Receptacle Interface Dimensions
90 Figure 5-2 – Example USB 3.1 Standard-A Receptacle with Grounding Springs and Required contact zones on the Standard-A Plug
91 Figure 5-3 – Example USB 3.1 Standard-A Mid-Mount Receptacles with Insertion Detect
94 Figure 5-4 – USB 3.1 Standard-A Plug Interface Dimensions
97 Figure 5-5 – Example Footprint for the USB 3.1 Standard-A Receptacle – Through-Hole with Back-Shield
98 Figure 5-6 – Example Footprint for the USB 3.1 Standard-A Receptacle – Mid-Mount Standard Mount Through-Hole with Insertion Detect
99 Figure 5-7 – Example Footprint for the USB 3.1 Standard-A Receptacle – Mid-Mount Reverse Mount Through-Hole with Insertion Detect
100 Table 5-2 – USB 3.1 Standard-A Connector Pin Assignments
101 5.3.2 USB 3.1 Standard-B Connector
Figure 5-8 – Illustration of Color Coding Recommendation for USB 3.1Standard-A Connector
103 Figure 5-9 – USB 3.1 Standard-B Receptacle Interface Dimensions
104 Figure 5-10 – USB 3.1 Standard-B Plug Interface Dimensions
105 Figure 5-11 – Reference Footprint for the USB 3.1 Standard-B Receptacle
106 5.3.3 USB 3.1 Micro Connector Family
Table 5-3 – USB 3.1 Standard-B Connector Pin Assignments
108 Figure 5-12 – USB 3.1 Micro-B and -AB Receptacles Interface Dimensions
111 Figure 5-13 – USB 3.1 Micro-B and Micro-A Plug Interface Dimensions
113 Figure 5-14 – Reference Footprint for the USB 3.1 Micro-B or Micro-AB Receptacle
114 5.4 Cable Construction and Wire Assignments
5.4.1 Cable Construction
Table 5-4 – USB 3.1 Micro-B Connector Pin Assignments
Table 5-5 – USB 3.1 Micro-AB/-A Connector Pin Assignments
115 5.4.2 Wire Assignments
Figure 5-15 – Illustration of a USB 3.1 Cable Cross-Section
116 5.4.3 Wire Gauges and Cable Diameters
5.5 Cable Assemblies
5.5.1 USB 3.1 Standard-A to USB 3.1 Standard-B Cable Assembly
Table 5-6 – Cable Wire Assignments
Table 5-7 – Reference Wire Gauges
117 Figure 5-16 – USB 3.1 Standard-A to USB 3.1 Standard-B Cable Assembly
118 5.5.2 USB 3.1 Standard-A to USB 3.1 Standard-A Cable Assembly
5.5.3 USB 3.1 Standard-A to USB 3.1 Micro-B Cable Assembly
Table 5-8 – USB 3.1 Standard-A to USB 3.1 Standard-B Cable Assembly Wiring
Table 5-9 – USB 3.1 Standard-A to USB 3.1 Standard-A Cable Assembly Wiring
119 Figure 5-17 – USB 3.1 Micro-B Plug Cable Overmold Dimensions
120 5.5.4 USB 3.1 Micro-A to USB 3.1 Micro-B Cable Assembly
Table 5-10 – USB 3.1 Standard-A to USB 3.1 Micro-B Cable Assembly Wiring
121 Figure 5-18 – USB 3.1 Micro-A Cable Overmold Dimensions
122 5.5.5 USB 3.1 Micro-A to USB 3.1 Standard-B Cable Assembly
Table 5-11 – USB 3.1 Micro-A to USB 3.1 Micro-B Cable Assembly Wiring
Table 5-12 – USB 3.1 Micro-A to USB 3.1 Standard-B Cable Assembly Wiring
123 5.5.6 USB 3.1 Icon Location
5.5.7 Cable Assembly Length
5.6 Electrical Requirements
Figure 5-19 – Typical Plug Orientation
124 5.6.1 Enhanced SuperSpeed Electrical Requirements
125 Figure 5-20 – Recommended Ground Void Dimension for USB Standard-A Receptacle
Table 5-13 – SDP Differential Insertion Loss Examples for Gen 2 speed
Table 5-14 – SDP Differential Insertion Loss Examples for Gen 2 speed with Coaxial Construction
126 Figure 5-21 – Impedance Limits of a Mated Connector for Gen 2 Speed
127 Figure 5-22 – Illustration of Cable Assembly Mounted on Test Fixture
Figure 5-23 – Illustration of Cable Assembly with Reference Host and Device
Table 5-15 – Design Targets
128 Figure 5-24 – Illustration of Insertion Loss Fit at Nyquist Frequency
129 Figure 5-25 – Example of Insertion Loss Deviation
131 Figure 5-26 – Pass/Fail Examples
132 Figure 5-27 – Illustration of Peak-to-Peak Crosstalk
Figure 5-28 – Differential-to-Common-Mode Conversion Requirement for Gen 2
133 5.6.2 DC Electrical Requirements
5.7 Mechanical and Environmental Requirements
Figure 5-29 – Set Up For Cable SE Measurement (subject to change)
134 5.7.1 Mechanical Requirements
Table 5-16 – Durability Ratings
136 Figure 5-30 – 4-Axes Continuity Test
137 5.7.2 Environmental Requirements
5.7.3 Materials
Table 5-17 – Environmental Test Conditions
138 5.8 Implementation Notes and Design Guides
5.8.1 Mated Connector Dimensions
Table 5-18 – Reference Materials
139 Figure 5-31 – Mated USB 3.1 Standard-A Connector
Figure 5-32 – Mated USB 3.1 Standard-B Connector
140 5.8.2 EMI and RFI Management
Figure 5-33 – Mated USB 3.1 Micro-B Connector
141 5.8.3 Stacked Connectors
Figure 5-34 – Examples of Connector Apertures
142 6 Physical Layer
6.1 Physical Layer Overview
6.2 Physical Layer Functions
Figure 6-1 – SuperSpeed Physical Layer
143 Figure 6-2 – Transmitter Block Diagram
144 Figure 6-3 – Gen 1 Receiver Block Diagram
145 Figure 6-4 – Gen 2 Receiver Block Diagram
146 6.2.1 Measurement Overview
6.2.2 Channel Overview
Figure 6-5 – Channel Models
147 6.3 Symbol Encoding
6.3.1 Gen 1 Encoding
Figure 6-6 – Character to Symbol Mapping
Figure 6-7 – Bit Transmission Order
148 Figure 6-8 – LFSR with Scrambling Polynomial
149 6.3.2 Gen 2 Encoding
Figure 6-9 – Gen 2 Serialization and Deserialization Order
150 Figure 6-10 – Gen 2 Bit Transmission Order and Framing
152 Figure 6-11 – LFSR for use in Gen 2 operation
153 6.3.3 Special Symbols for Framing and Link Management
Table 6-1 – Special Symbols
154 6.4 Link Initialization and Training
6.4.1 Link Training
155 Table 6-2 – Gen 1 TSEQ Ordered Set
Table 6-3 – Gen 1 TS1 Ordered Set
Table 6-4 – Gen 1 TS2 Ordered Set
156 Table 6-5 – Gen 1/Gen 2 Link Configuration
157 Table 6-6 – Gen 2 TS1 Ordered Set
158 Table 6-7 – Gen 2 TS2 Ordered Set
Table 6-8 – Gen 2 TSEQ Ordered Set
Table 6-9 – Gen 2 SYNC Ordered Set
Table 6-10 – SDS Ordered Set
159 6.4.2 Lane Polarity Inversion
6.4.3 Elasticity Buffer and SKP Ordered Set
160 Table 6-11 – Gen 1 SKP Ordered Set Structure
161 6.4.4 Compliance Pattern
Table 6-12 – Gen 2 SKP Ordered Set
162 6.5 Clock and Jitter
6.5.1 Informative Jitter Budgeting
Table 6-13 – Compliance Pattern Sequences
Table 6-14 – Gen 2 Compliance Pattern
163 6.5.2 Normative Clock Recovery Function
Figure 6-12 – Jitter Filtering – “Golden PLL” and Jitter Transfer Functions
Table 6-15 – Informative Jitter Budgeting at the Silicon Pads
164 Figure 6-13 – “Golden PLL” and Jitter Transfer Functions for Gen 1 Operation
Figure 6-14 – “Golden PLL” and Jitter Transfer Functions for Gen 2 Operation
165 6.5.3 Normative Spread Spectrum Clocking (SSC)
Figure 6-15 – Example of Period Modulation from Triangular SSC
Table 6-16 – SSC Parameters
166 6.5.4 Normative Slew Rate Limit
6.6 Signaling
6.6.1 Eye Diagrams
167 6.6.2 Voltage Level Definitions
Figure 6-16 – Eye Masks
168 6.6.3 Tx and Rx Input Parasitics
6.7 Transmitter Specifications
6.7.1 Transmitter Electrical Parameters
Figure 6-17 – Single-ended and Differential Voltage Levels
Figure 6-18 – Device Termination Schematic
169 Table 6-17 – Transmitter Normative Electrical Parameters
170 6.7.2 Low Power Transmitter
6.7.3 Transmitter Eye
Table 6-18 – Transmitter Informative Electrical Parameters at Silicon Pads
171 6.7.4 Tx Compliance Reference Receiver Equalize Function
6.7.5 Informative Transmitter De-emphasis
Figure 6-19 – Tx Normative Setup with Reference Channel
Table 6-19 – Normative Transmitter Eye Mask at Test Point TP1
172 Figure 6-20 – De-Emphasis Waveform
Figure 6-21 – 3-tap Transmit Equalizer Structure
173 6.7.6 Entry into Electrical Idle, U1
6.8 Receiver Specifications
6.8.1 Receiver Equalization Training
Figure 6-22 – Example Output Waveform for 3-tap Transmit Equalizer
Table 6-20 – Informative Gen 2 Transmitter Equalization Settings
174 6.8.2 Informative Receiver CTLE Function
Figure 6-23 – Frequency Spectrum of TSEQ
175 Figure 6-24 – Gen 1 Tx Compliance Rx EQ Transfer Function
176 Figure 6-25 – Gen 2 Compliance Rx EQ Transfer Function
177 6.8.3 Receiver Electrical Parameters
Figure 6-26 – Gen 2 reference DFE Function
Table 6-21 – Receiver Normative Electrical Parameters
178 6.8.4 Receiver Loopback
Table 6-22 – Receiver Informative Electrical Parameters
179 6.8.5 Normative Receiver Tolerance Compliance Test
Table 6-23 – BRST
Table 6-24 – BDAT
Table 6-25 – BERC
Table 6-26 – BCNT
180 Figure 6-27 – Rx Tolerance Setup
Figure 6-28 – Jitter Tolerance Curve
181 6.9 Low Frequency Periodic Signaling (LFPS)
6.9.1 LFPS Signal Definition
Table 6-27 – Input Jitter Requirements for Rx Tolerance Testing
182 Figure 6-29 – LFPS Signaling
Table 6-28 – Normative LFPS Electrical Specification
183 6.9.2 Example LFPS Handshake for U1/U2 Exit, Loopback Exit, and U3 Wakeup
Table 6-29 – LFPS Transmitter Timing for SuperSpeed Designs1
184 Figure 6-30 – U1 Exit, U2 Exit, and U3 Wakeup LFPS Handshake Timing Diagram
185 6.9.3 Warm Reset
Table 6-30 – LFPS Handshake Timing for U1/U2 Exit, Loopback Exit, and U3 Wakeup
186 6.9.4 SuperSpeedPlus Capability Declaration
Figure 6-31 – Example of Warm Reset Out of U3
Figure 6-32 – Example of Binary Representation based on Polling.LFPS
Table 6-31 – Binary Representation of Polling.LFPS
187 6.9.5 SuperSpeedPlus LFPS Based PWM Message (LBPM)
Figure 6-33 – SCD1/SCD2 transmission
188 Figure 6-34 – Logic Representation of LBPS
Table 6-32 – LBPS Transmit and Receive Specification
189 6.10 Transmitter and Receiver DC Specifications
6.10.1 Informative ESD Protection
6.10.2 Informative Short Circuit Requirements
6.10.3 Normative High Impedance Reflections
6.11 Receiver Detection
6.11.1 Rx Detect Overview
Figure 6-35 – LBPM Transmission Examples
190 6.11.2 Rx Detect Sequence
6.11.3 Upper Limit on Channel Capacitance
Figure 6-36 – Rx Detect Schematic
191 6.12 Retimers
7 Link Layer
Figure 7-1 – Link Layer
192 7.1 Byte Ordering
7.1.1 SuperSpeed USB Line Code
7.1.2 SuperSpeedPlus USB Line Code
7.2 Link Management and Flow Control
Figure 7-2 – Byte Ordering
193 7.2.1 Packets and Packet Framing
Figure 7-3 – Enhanced SuperSpeed Header Packet with HPSTART, Packet Header, and Link Control Word
194 Figure 7-4 – SuperSpeedPlus DPH Format
Figure 7-5 – Packet Header
195 Figure 7-6 – CRC-16 Remainder Generation
Table 7-1 – CRC-16 Mapping
196 Figure 7-7 – Link Control Word
Figure 7-8 – CRC-5 Remainder Generation
197 Figure 7-9 – Data Packet Payload with CRC-32 and Framing
198 Figure 7-10 – CRC-32 Remainder Generation
199 Table 7-2 – CRC-32 Mapping
200 Figure 7-11 – Data Packet with Data Packet Header Followed byData Packet Payload. (a) SuperSpeed DP; (b). SuperSpeedPlus DP
201 7.2.2 Link Commands
Figure 7-12 – Link Command Structure
Figure 7-13 – Link Command Word Structure
Table 7-3 – Link Command Ordered Set Structure
202 Table 7-4 – Link Command Bit Definitions
204 Table 7-5 – Link Command Definitions
205 7.2.3 Logical Idle
7.2.4 Link Command Usage for Flow Control, Error Recovery, and Power Management
Table 7-6 – Logical Idle Definition
216 Table 7-7 – Transmitter Timers Summary
217 Table 7-8 – Link Flow Control Timers Summary
221 7.3 Link Error Rules/Recovery
7.3.1 Overview of Enhanced SuperSpeed Bit Errors
7.3.2 Link Error Types, Detection, and Recovery
7.3.3 Link Error Statistics
222 7.3.4 Header Packet Errors
223 7.3.5 Link Command Errors
Table 7-9 – Valid Packet Framing Symbol Order (Sx is One of SHP, DPHP, SDP, END or EDB)
224 7.3.6 ACK Tx Header Sequence Number Error
Table 7-10 – Valid Link Command Symbol Order
225 7.3.7 Header Sequence Number Advertisement Error
7.3.8 SuperSpeed Rx Header Buffer Credit Advertisement Error
226 7.3.9 SuperSpeedPlus Type 1/Type 2 Rx Buffer Credit Advertisement Error
7.3.10 Training Sequence Error
227 7.3.11 SuperSpeed 8b/10b Errors
7.3.12 SuperSpeedPlus Block Header Errors
7.3.13 Summary of Error Types and Recovery
228 Table 7-11 – Error Types and Recovery
229 7.4 PowerOn Reset and Inband Reset
7.4.1 PowerOn Reset
230 7.4.2 Inband Reset
231 7.5 Link Training and Status State Machine (LTSSM)
232 Table 7-12 – LTSSM State Transition Timeouts
233 7.5.1 eSS.Disabled
Figure 7-14 – State Diagram of the Link Training and Status State Machine
235 7.5.2 eSS.Inactive
Figure 7-15 – eSS.Disabled Substate Machine
236 7.5.3 Rx.Detect
Figure 7-16 – eSS.Inactive Substate Machine
239 7.5.4 Polling
Figure 7-17 – Rx.Detect Substate Machine
243 Table 7-13 – PHY Capability LBPM
250 7.5.5 Compliance Mode
Figure 7-18 – Polling Substate Machine
251 7.5.6 U0
252 7.5.7 U1
253 7.5.8 U2
Figure 7-19 – U1
254 7.5.9 U3
Figure 7-20 – U2
255 7.5.10 Recovery
Figure 7-21 – U3
259 7.5.11 Loopback
Figure 7-22 – Recovery Substate Machine
261 7.5.12 Hot Reset
Figure 7-23 – Loopback Substate Machine
263 8 Protocol Layer
Figure 7-24 – Hot Reset Substate Machine
264 8.1 Enhanced SuperSpeed Transactions
8.1.1 Transactions on a SuperSpeed Bus Instance
Figure 8-1 – Protocol Layer Highlighted
265 8.1.2 Transactions on a SuperSpeedPlus Bus Instance
266 8.2 Packet Types
8.3 Packet Formats
8.3.1 Fields Common to all Headers
Figure 8-2 – Example Transaction Packet
267 Figure 8-3 – Link Control Word Detail
Table 8-1 – Type Field Description
268 8.4 Link Management Packet (LMP)
8.4.1 Subtype Field
Figure 8-4 – Link Management Packet Structure
Table 8-2 – Link Control Word Format
269 8.4.2 Set Link Function
Figure 8-5 – Set Link Function LMP
Table 8-3 – Link Management Packet Subtype Field
270 8.4.3 U2 Inactivity Timeout
8.4.4 Vendor Device Test
Figure 8-6 – U2 Inactivity Timeout LMP
Figure 8-7 – Vendor Device Test LMP
Table 8-4 – Set Link Function
Table 8-5 – U2 Inactivity Timer Functionality
271 8.4.5 Port Capabilities
Figure 8-8 – Port Capability LMP
Table 8-6 – Vendor-specific Device Test Function
272 Table 8-7 – Port Capability LMP Format
Table 8-8 – Port Type Selection Matrix
273 8.4.6 Port Configuration
8.4.7 Port Configuration Response
Figure 8-9 – Port Configuration LMP
Table 8-9 – Port Configuration LMP Format (Differences with Port Capability LMP)
274 8.4.8 Precision Time Measurement
Figure 8-10 – Port Configuration Response LMP
Table 8-10 – Port Configuration Response LMP Format (Differences with Port Capability LMP)
275 Figure 8-11 – Link Delay Measurement Protocol
276 Figure 8-12 – PTM ITP Protocol
277 Figure 8-13 – LDM State Machine Notation
278 Figure 8-14 – LDM Requester State Machine
280 Figure 8-15 – LDM Responder State Machine
284 Figure 8-16 – PTM Path Performance Contributors
286 Figure 8-17 – LDM LMP
287 8.5 Transaction Packet (TP)
8.5.1 Acknowledgement (ACK) Transaction Packet
Table 8-11 – LDM LMP
Table 8-12 – Transaction Packet Subtype Field
288 Figure 8-18 – ACK Transaction Packet
289 Table 8-13 – ACK TP Format
290 8.5.2 Not Ready (NRDY) Transaction Packet
291 8.5.3 Endpoint Ready (ERDY) Transaction Packet
Figure 8-19 – NRDY Transaction Packet
Figure 8-20 – ERDY Transaction Packet
Table 8-14 – NRDY TP Format (Differences with ACK TP)
Table 8-15 – ERDY TP Format (Differences with ACK TP)
292 8.5.4 STATUS Transaction Packet
8.5.5 STALL Transaction Packet
8.5.6 Device Notification (DEV_NOTIFICATION) Transaction Packet
Figure 8-21 – STATUS Transaction Packet
Figure 8-22 – STALL Transaction Packet
Table 8-16 – STATUS TP Format (Differences with ACK TP)
Table 8-17 – STALL TP Format (Differences with ACK TP)
293 Figure 8-23 – Device Notification Transaction Packet
Figure 8-24 – Function Wake Device Notification
Table 8-18 – Device Notification TP Format (Differences with ACK TP)
294 Figure 8-25 – Latency Tolerance Message Device Notification
Table 8-19 – Function Wake Device Notification
Table 8-20 – Latency Tolerance Message Device Notification
295 Figure 8-26 – Bus Interval Adjustment Message Device Notification
Table 8-21 – Bus Interval Adjustment Message Device Notification
298 Figure 8-27 – Sublink Speed Device Notification
Table 8-22 – Sublink Speed Device Notification
299 8.5.7 PING Transaction Packet
8.5.8 PING_RESPONSE Transaction Packet
Figure 8-28 – PING Transaction Packet
Table 8-23 – PING TP Format (differences with ACK TP)
300 8.6 Data Packet (DP)
Figure 8-29 – PING_RESPONSE Transaction Packet
Figure 8-30 – Example Data Packet
Table 8-24 – PING_RESPONSE TP Format (Differences with ACK TP)
301 Table 8-25 – Data Packet Format (Differences with ACK TP)
302 8.7 Isochronous Timestamp Packet (ITP)
Figure 8-31 – Isochronous Timestamp Packet
Table 8-26 – Isochronous Timestamp Packet Format
303 8.8 Addressing Triple
8.9 Route String Field
8.9.1 Route String Port Field
8.9.2 Route String Port Field Width
8.9.3 Port Number
8.10 Transaction Packet Usages
Figure 8-32 – Route String Detail
304 8.10.1 Flow Control Conditions
8.10.2 Burst Transactions
306 8.10.3 Short Packets
8.10.4 SuperSpeedPlus Transaction Reordering
307 Figure 8-33 – Sample Concurrent BULK IN Transactions
308 8.11 TP or DP Responses
Figure 8-34 – Sample Concurrent BULK and Isochronous IN Transactions
309 8.11.1 Device Response to TP Requesting Data
8.11.2 Host Response to Data Received from a Device
Table 8-27 – Device Responses to TP Requesting Data (Bulk, Control, and Interrupt Endpoints)
310 8.11.3 Device Response to Data Received from the Host
Table 8-28 – Host Responses to Data Received from a Device (Bulk, Control, and Interrupt Endpoints)
311 8.11.4 Device Response to a SETUP DP
Table 8-29 – Device Responses to OUT Transactions (Bulk, Control, and Interrupt Endpoints)
312 8.12 TP Sequences
8.12.1 Bulk Transactions
Table 8-30 – Device Responses to SETUP Transactions (Only for Control Endpoints)
313 Figure 8-35 – Legend for State Machines
315 Figure 8-36 – Sample BULK IN Sequence
316 Figure 8-37 – Sample BULK OUT Sequence
317 Figure 8-38 – General Stream Protocol State Machine (SPSM)
320 Figure 8-39 – Device IN Stream Protocol State Machine (DISPSM)
323 Figure 8-40 – Device IN Move Data State Machine (DIMDSM)
325 Figure 8-41 – Device OUT Stream Protocol State Machine (DOSPSM)
328 Figure 8-42 – Device OUT Move Data State Machine (DOMDSM)
331 Figure 8-43 – Host IN Stream Protocol State Machine (HISPSM)
333 Figure 8-44 – Host IN Move Data State Machine (HIMDSM)
336 Figure 8-45 – Host OUT Stream Protocol State Machine (HOSPSM)
339 Figure 8-46 – Host OUT Move Data State Machine (HOMDSM)
341 8.12.2 Control Transfers
342 Figure 8-47 – Control Read Sequence
343 Figure 8-48 – Control Write Sequence
344 8.12.3 Bus Interval and Service Interval
8.12.4 Interrupt Transactions
Table 8-31 – Status Stage Responses
346 Figure 8-49 – Host Sends Interrupt IN Transaction in Each Service Interval
Figure 8-50 – Host Stops Servicing Interrupt IN Transaction Once NRDY is Received
347 Figure 8-51 – Host Resumes IN Transaction after Device Sent ERDY
Figure 8-52 – Endpoint Sends STALL TP
Figure 8-53 – Host Detects Error in Data and Device Resends Data
349 Figure 8-54 – Host Sends Interrupt OUT Transaction in Each Service Interval
Figure 8-55 – Host Stops Servicing Interrupt OUT Transaction Once NRDY is Received
Figure 8-56 – Host Resumes Sending Interrupt OUT Transaction After Device Sent ERDY
350 8.12.5 Host Timing Information
Figure 8-57 – Device Detects Error in Data and Host Resends Data
Figure 8-58 – Endpoint Sends STALL TP
351 8.12.6 Isochronous Transactions
Figure 8-59 – Multiple Active Isochronous Endpoints withAligned Service Interval Boundaries
352 Figure 8-60 – Enhanced SuperSpeed Isochronous IN Transaction Format
Figure 8-61 – Enhanced SuperSpeed Isochronous OUT Transaction Format
353 Figure 8-62 – Sample Enhanced SuperSpeed Isochronous IN Transaction
354 Figure 8-63 – Sample Enhanced SuperSpeed Isochronous OUT Transaction
355 Figure 8-64 – Sample Enhanced SuperSpeed Isochronous IN Transaction
356 Figure 8-65 – Sample Enhanced SuperSpeed Isochronous OUT Transaction
358 Figure 8-66 – Sample Smart Enhanced SuperSpeed Isochronous IN Transaction
359 Figure 8-67 – Sample Smart Enhanced SuperSpeed Isochronous OUT Transaction
360 Table 8-32 – ACK TP and DPs for Pipelined Isochronous IN Transactions
361 Figure 8-68 – Sample Pipeline Isochronous IN Transactions
362 Table 8-33 – Device Responses to Isochronous IN Transactions
363 8.13 Timing Parameters
Table 8-34 – Host Responses to IN Transactions
Table 8-35 – Device Responses to OUT Data Packets
364 Table 8-36 – Timing Parameters
366 9 Device Framework
9.1 USB Device States
9.1.1 Visible Device States
367 Figure 9-1 – Peripheral State Diagram and Hub State Diagram (Enhanced SuperSpeed Portion Only)
368 Table 9-1 – Visible Enhanced SuperSpeed Device States
371 9.1.2 Bus Enumeration
372 9.2 Generic Device Operations
9.2.1 Dynamic Attachment and Removal
9.2.2 Address Assignment
9.2.3 Configuration
373 9.2.4 Data Transfer
9.2.5 Power Management
374 Table 9-2 – Preserved USB Suspend State Parameters
375 9.2.6 Request Processing
377 9.2.7 Request Error
9.3 USB Device Requests
9.3.1 bmRequestType
Table 9-3 – Format of Setup Data
378 9.3.2 bRequest
9.3.3 wValue
9.3.4 wIndex
9.3.5 wLength
Figure 9-2 – wIndex Format when Specifying an Endpoint
Figure 9-3 – wIndex Format when Specifying an Interface
379 9.4 Standard Device Requests
Table 9-4 – Standard Device Requests
380 Table 9-5 – Standard Request Codes
381 Table 9-6 – Descriptor Types
Table 9-7 – Standard Feature Selectors
382 9.4.1 Clear Feature
9.4.2 Get Configuration
383 9.4.3 Get Descriptor
384 9.4.4 Get Interface
9.4.5 Get Status
385 Figure 9-4 – Information Returned by a Standard GetStatus() Request to a Device
Table 9-8 – Standard Status Type Codes
386 Figure 9-5 – Information Returned by a Standard GetStatus() Request to an Interface
Figure 9-6 – Information Returned by a Standard GetStatus() Request to an Endpoint
387 9.4.6 Set Address
Figure 9-7 – Information Returned by a PTM GetStatus() Request to an Endpoint
388 9.4.7 Set Configuration
9.4.8 Set Descriptor
389 9.4.9 Set Feature
390 9.4.10 Set Interface
Table 9-9 – Suspend Options
391 9.4.11 Set Isochronous Delay
9.4.12 Set SEL
392 9.4.13 Synch Frame
9.4.14 Events and Their Effect on Device Parameters
393 9.5 Descriptors
Table 9-10 – Device Parameters and Events
394 9.6 Standard USB Descriptor Definitions
9.6.1 Device
396 Table 9-11 – Standard Device Descriptor
397 9.6.2 Binary Device Object Store (BOS)
Table 9-12 – BOS Descriptor
Table 9-13 – Format of a Device Capability Descriptor
398 Table 9-14 – Device Capability Type Codes
Table 9-15 – USB 2.0 Extension Descriptor
400 Table 9-16 – SuperSpeed Device Capability Descriptor
401 Table 9-17 – Container ID Descriptor
402 Table 9-18 – Platform Descriptor
403 Table 9-19 – SuperSpeedPlus Descriptor
405 9.6.3 Configuration
Table 9-20 – PTM Capability Descriptor
406 9.6.4 Interface Association
Table 9-21 – Standard Configuration Descriptor
407 9.6.5 Interface
Table 9-22 – Standard Interface Association Descriptor
409 9.6.6 Endpoint
Table 9-23 – Standard Interface Descriptor
410 Table 9-24 – Standard Endpoint Descriptor
411 Table 9-25 – Example of Feedback Endpoint Numbers
412 9.6.7 SuperSpeed Endpoint Companion
Figure 9-8 – Example of Feedback Endpoint Relationships
413 Table 9-26 – SuperSpeed Endpoint Companion Descriptor
414 9.6.8 SuperSpeedPlus Isochronous Endpoint Companion
Table 9-27 – SuperSpeedPlus Isochronous Endpoint Companion Descriptor
415 9.6.9 String
9.7 Device Class Definitions
9.7.1 Descriptors
Table 9-28 – String Descriptor Zero, Specifying Languages Supported by the Device
Table 9-29 – UNICODE String Descriptor
416 9.7.2 Interface(s)
9.7.3 Requests
10 Hub, Host Downstream Port, and Device Upstream Port Specification
10.1 Hub Feature Summary
417 Figure 10-1 – USB Hub Architecture
418 Figure 10-2 – SuperSpeed Portion of the USB Hub Architecture
419 Figure 10-3 – SuperSpeedPlus Portion of the Hub Architecture
420 10.1.1 Connecting to an Enhanced SuperSpeed Capable Host
10.1.2 Connecting to a USB 2.0 Host
Figure 10-4 – Simple USB Topology
421 10.1.3 Hub Connectivity
422 Figure 10-5 – Route String Example
423 10.1.4 Resume Connectivity
Figure 10-6 – SuperSpeed Hub Signaling Connectivity
424 10.1.5 Hub Fault Recovery Mechanisms
10.1.6 Hub Buffer Architecture
Figure 10-7 – Resume Connectivity
425 Figure 10-8 – Typical SuperSpeed Hub Header Packet Buffer Architecture
Figure 10-9 – SuperSpeed Hub Data Buffer Traffic (Header Packet Buffer Only Shown for DS Port 1)
426 10.2 Hub Power Management
10.2.1 Link States
10.2.2 Hub Downstream Port U1/U2 Timers
10.2.3 Downstream/Upstream Port Link State Transitions
427 10.3 Hub Downstream Facing Ports
428 Figure 10-10 – Downstream Facing Hub Port State Machine
429 Table 10-1 – Downstream Facing Hub Port State Machine Diagram Legend
430 10.3.1 Hub Downstream Facing Port State Descriptions
431 Table 10-2 – Downstream Port Vbus Requirements
434 10.3.2 Disconnect Detect Mechanism
435 10.3.3 Labeling
10.4 Hub Downstream Facing Port Power Management
10.4.1 Downstream Facing Port PM Timers
436 10.4.2 Hub Downstream Facing Port State Descriptions
Figure 10-11 – Downstream Facing Hub Port Power Management State Machine
439 10.5 Hub Upstream Facing Port
440 10.5.1 Upstream Facing Port State Descriptions
Figure 10-12 – Upstream Facing Hub Port State Machine
442 10.5.2 Hub Connect State Machine
Figure 10-13 – Hub Connect (HCONNECT) State Machine
443 10.6 Upstream Facing Port Power Management
444 10.6.1 Upstream Facing Port PM Timer
Figure 10-14 – Upstream Facing Hub Port Power Management State Machine
445 10.6.2 Hub Upstream Facing Port State Descriptions
447 10.7 SuperSpeed Hub Header Packet Forwarding and Data Repeater
448 10.7.1 SuperSpeed Hub Elasticity Buffer
10.7.2 SKP Ordered Sets
10.7.3 Interpacket Spacing
10.7.4 SuperSpeed Header Packet Buffer Architecture
Figure 10-15 – Example SS Hub Header Packet Buffer Architecture – Downstream Traffic
449 10.7.5 SuperSpeed Packet Connectivity
Figure 10-16 – Example SS Hub Header Packet Buffer Architecture – Upstream Traffic
450 10.8 SuperSpeedPlus Store and Forward Behavior
10.8.1 Hub Elasticity Buffer
10.8.2 SKP Ordered Sets
10.8.3 Interpacket Spacing
10.8.4 Upstream Flowing Buffering
451 10.8.5 Downstream Flowing Buffering
Figure 10-17 – Logical Representation of Upstream Flowing Buffers
Figure 10-18 – Logical Representation of Downstream Flowing Buffers
452 10.8.6 SuperSpeedPlus Hub Arbitration of Packets
454 10.8.7 SuperSpeedPlus Upstream Flowing Packet Modifications
455 10.8.8 SuperSpeedPlus Downstream Controller
10.9 Port State Machines
10.9.1 Port Transmit State Machine
456 10.9.2 Port Transmit State Descriptions
Figure 10-19 – Port Transmit State Machine
457 10.9.3 Port Receive State Machine
458 10.9.4 Port Receive State Descriptions
Figure 10-20 – Upstream Facing Port Rx State Machine
459 Table 10-3 – Downstream Flowing Header Packet Processing Actions
463 10.10 Suspend and Resume
10.11 Hub Upstream Port Reset Behavior
464 10.12 Hub Port Power Control
10.12.1 Multiple Gangs
10.13 Hub Controller
465 10.13.1 Endpoint Organization
10.13.2 Hub Information Architecture and Operation
Figure 10-21 – Example Hub Controller Organization
466 10.13.3 Port Change Information Processing
Figure 10-22 – Relationship of Status, Status Change, and Control Information to Device States
467 10.13.4 Hub and Port Status Change Bitmap
Figure 10-23 – Port Status Handling Method
468 10.13.5 Over-current Reporting and Recovery
Figure 10-24 – Hub and Port Status Change Bitmap
Figure 10-25 – Example Hub and Port Change Bit Sampling
469 10.13.6 Enumeration Handling
10.14 Hub Configuration
470 10.15 Descriptors
Table 10-4 – Hub Power Operating Mode Summary
471 10.15.1 Standard Descriptors for Hub Class
476 10.15.2 Class-specific Descriptors
477 Table 10-5 – Enhanced SuperSpeed Hub Descriptor
478 10.16 Requests
10.16.1 Standard Requests
479 10.16.2 Class-specific Requests
Table 10-6 – Hub Responses to Standard Device Requests
480 Table 10-7 – Hub Class Requests
Table 10-8 – Hub Class Request Codes
481 Table 10-9 – Hub Class Feature Selectors
483 Table 10-10 – Hub Status Field, wHubStatus
484 Table 10-11 – Hub Change Field, wHubChange
485 Table 10-12 – Port Status Type Codes
486 Table 10-13 – Port Status Field, wPortStatus
489 Table 10-14 – Port Change Field, wPortChange
491 Table 10-15 – Extended Port Status Field, dwExtPortStatus
493 Table 10-16 – U1 Timeout Value Encoding
Table 10-17 – U2 Timeout Value Encoding
495 Table 10-18 – Downstream Port Remote Wake Mask Encoding
496 10.17 Host Root (Downstream) Ports
10.18 Peripheral Device Upstream Ports
10.18.1 Peripheral Device Upstream Ports
497 10.18.2 Peripheral Device Upstream Port State Machine
Figure 10-26 – Peripheral Upstream Device Port State Machine
499 10.19 Hub Chapter Parameters
500 Table 10-19 – Hub Parameters
501 11 Interoperability and Power Delivery
502 11.1 USB 3.1 Host Support for USB 2.0
11.2 USB 3.1 Hub Support for USB 2.0
Table 11-1 – USB 3.0 and USB 2.0 Interoperability
503 11.3 USB 3.1 Device Support for USB 2.0
11.4 Power Distribution
11.4.1 Classes of Devices and Connections
504 Figure 11-1 – Compound Self-powered Hub
505 Figure 11-2 – Low-power Bus-powered Function
Figure 11-3 – High-power Bus-powered Function
506 11.4.2 Steady-State Voltage Drop Budget
Figure 11-4 – Self-powered Function
Figure 11-5 – Worst-case Voltage Drop Topology (Steady State)
507 11.4.3 Power Control During Suspend/Resume
Figure 11-6 – Worst-case Voltage Drop Analysis Using Equivalent Resistance
508 11.4.4 Dynamic Attach and Detach
Figure 11-7 – Typical Suspend Current Averaging Profile
509 11.4.5 Vbus Electrical Characteristics
11.4.6 Powered-B Connector
11.4.7 Wire Gauge Table
Table 11-2 – DC Electrical Characteristics
510 Table 11-3 – Vbus/Gnd Wire Gauge vs. Maximum Length
511 Table A.1 – 8b/10b Data Symbol Codes
517 Table A.2 – 8b/10b Special Character Symbol Codes
525 Table C.1 – Link States and Characteristics Summary
534 Figure C.1 – Flow Diagram for Host Initiated Wakeup
535 Figure C.2 – Device Total Intrinsic Latency Tolerance
537 Figure C.3 – Host to Device Path Exit Latency Calculation Examples
538 Figure C.4 – Device Connected Directly to a Host
539 Figure C.5 – Device Connected Through a Hub
540 Figure C.6 – Downstream Host to Device Path Exit Latency with Hub
541 Figure C.7 – Upstream Device to Host Path Exit Latency with Hub
544 Figure C.8 – LT State Diagram
547 Figure C.9 – System Power during SuperSpeed and High Speed Device Data Transfers
548 Figure D.1 – Sample ERDY Transaction Packet
Figure D.2 – Sample Data Packet
Figure D.3 – Example placement of Gen 2 SKP Block, Idle Symbols, Link Command and Header Packet
549 Figure D.4 – Example placement of Gen 2 Data Packets and Idle Symbols
550 Figure E.1 – Link segment definition
551 Figure E.2 – Retimer implementation examples
552 Figure E.3 – Example high level retimer architecture in Gen 2 operation
555 Figure E.4 – Retimer Training and Status State Machine
557 Figure E.5 – Polling Substate Machine
565 Figure E.6 – Recovery Substate Machine
568 Figure E.7 – Example block diagram of a retimer operating at SuperSpeed
571 Table 6-13 – Compliance Pattern Sequences
572 Table 6-13 – Compliance Pattern Sequences
573 Table 6-17 – Transmitter Normative Electrical Parameters
574 Table 6-17 – Transmitter Normative Electrical Parameters
575 Figure 6-20 – De-Emphasis Waveform
576 Figure 6-21 – 3-tap Transmit Equalizer Structure
Figure 6-22 – Example Output Waveform for 3-tap Transmit Equalizer
577 Table 6-20 – Informative Gen 2 Transmitter Equalization Settings
578 Figure 6-20 – De-Emphasis Waveform
579 Figure 6-21 – 3-tap Transmit Equalizer Structure
Figure 6-22 – Example Output Waveform for 3-tap Transmit Equalizer
580 Table 6-20 – Informative Gen 2 Transmitter Equalization Settings
581 Figure 6-23 – Example waveforms for measuring transmitter equalization
582 Figure 6-25 – Gen 2 Compliance Rx EQ Transfer Function
583 Figure 6-25 – Gen 2 Compliance Rx EQ Transfer Function
584 Table 6-27 – Input Jitter Requirements for Rx Tolerance Testing
585 Table 6-27 – Input Jitter Requirements for Rx Tolerance Testing
590 Table 11-4 – Link Command Bit Definitions
591 Table 11-5 – Link Command Bit Definitions
613 Table 11-6 – Gen 2 SKP Ordered Set
614 Table 11-7 – Gen 2 SKP Ordered Set
619 Table 11-8 – SDS Ordered Set
620 Table 11-9 – SDS Ordered Set
622 Table 6-29 – LFPS Transmitter Timing for SuperSpeed Designs1
Table 6-29 – LFPS Transmitter Timing for SuperSpeed Designs1
624 Table 6-15 – Informative Jitter Budgeting at the Silicon Pads
Table 6-15 – Informative Jitter Budgeting at the Silicon Pads
625 Table 6-19 – Normative Transmitter Eye Mask at Test Point TP1
Table 6-19 – Normative Transmitter Eye Mask at Test Point TP1
626 Table 6-27 – Input Jitter Requirements for Rx Tolerance Testing
627 Table 6-27 – Input Jitter Requirements for Rx Tolerance Testing

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BS EN 62680-3-1:2017
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