BS EN 60749-21:2011
$142.49
Semiconductor devices. Mechanical and climatic test methods – Solderability
Published By | Publication Date | Number of Pages |
BSI | 2011 | 26 |
This part of IEC 60749 establishes a standard procedure for determining the solderability of device package terminations that are intended to be joined to another surface using tin-lead (SnPb) or lead-free (Pb-free) solder for the attachment.
This test method provides a procedure for ‘dip and look’ solderability testing of through hole, axial and surface mount devices (SMDs) as well as an optional procedure for a board mounting solderability test for SMDs for the purpose of allowing simulation of the soldering process to be used in the device application. The test method also provides optional conditions for ageing.
This test is considered destructive unless otherwise detailed in the relevant specification.
NOTE 1 This test method is in general accord with IEC 60068, but due to specific requirements of semiconductors, the following text is applied.
NOTE 2 This test method does not assess the effect of thermal stresses which may occur during the soldering process. Reference should be made IEC 60749-15 or IEC 60749-20.
PDF Catalog
PDF Pages | PDF Title |
---|---|
6 | English CONTENTS |
8 | 1 Scope 2 Normative references 3 Test apparatus 3.1 Solder bath 3.2 Dipping device |
9 | 3.3 Optical equipment 3.4 Steam ageing equipment 3.5 Lighting equipment 3.6 Materials |
10 | 3.7 SMD reflow equipment |
11 | 4 Procedure 4.1 Lead-free backward compatibility |
12 | 4.2 Preconditioning Tables Table 1 – Steam ageing conditions Table 2 – Altitude versus steam temperature |
13 | 4.3 Procedure for dip and look solderability testing Table 3 – Solder dip test conditions |
15 | Table 4 – Maximum limits of solder bath contaminant |
17 | Figures Figure 1 – Areas to be inspected for gullwing packages |
18 | Figure 2 – Areas to be inspected for J-lead packages |
19 | Figure 3 – Areas to be inspected in rectangular components (SMD method) |
20 | Figure 4 – Areas to be inspected in SOIC and QFP packages (SMD method) |
21 | 4.4 Procedure for simulated board mounting reflow solderability testing of SMDs |
22 | Figure 5 – Flat peak type reflow profile |
23 | 5 Summary |
24 | Bibliography |