{"id":409813,"date":"2024-10-20T05:37:25","date_gmt":"2024-10-20T05:37:25","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-iec-61131-92022\/"},"modified":"2024-10-26T10:19:53","modified_gmt":"2024-10-26T10:19:53","slug":"bs-en-iec-61131-92022","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-iec-61131-92022\/","title":{"rendered":"BS EN IEC 61131-9:2022"},"content":{"rendered":"

This part of IEC 61131 specifies a single-drop digital communication interface technology for small sensors and actuators SDCI (commonly known as IO-LinkTM2), which extends the traditional digital input and digital output interfaces as defined in IEC 61131-2 towards a point-to-point communication link. This technology enables the transfer of parameters to Devices and the delivery of diagnostic information from the Devices to the automation system. This technology is mainly intended for use with simple sensors and actuators in factory automation, which include small and cost-effective microcontrollers. This part specifies the SDCI communication services and protocol (physical layer, data link layer and application layer in accordance with the ISO\/OSI reference model) for both SDCI Masters and Devices. This part also includes EMC test requirements. This part does not cover communication interfaces or systems incorporating multiple point or multiple drop linkages, or integration of SDCI into higher level systems such as fieldbuses.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
2<\/td>\nundefined <\/td>\n<\/tr>\n
5<\/td>\nAnnex ZA (normative)Normative references to international publicationswith their corresponding European publications <\/td>\n<\/tr>\n
7<\/td>\nEnglish
CONTENTS <\/td>\n<\/tr>\n
25<\/td>\nFOREWORD <\/td>\n<\/tr>\n
27<\/td>\nINTRODUCTION <\/td>\n<\/tr>\n
29<\/td>\n1 Scope
2 Normative references <\/td>\n<\/tr>\n
30<\/td>\n3 Terms, definitions, symbols, abbreviated terms, and conventions
3.1 Terms and definitions <\/td>\n<\/tr>\n
34<\/td>\n3.2 Symbols and abbreviated terms <\/td>\n<\/tr>\n
36<\/td>\n3.3 Conventions
3.3.1 General <\/td>\n<\/tr>\n
37<\/td>\n3.3.2 Service parameters
3.3.3 Service procedures
3.3.4 Service attributes <\/td>\n<\/tr>\n
38<\/td>\n3.3.5 Figures
3.3.6 Tables
3.3.7 Transmission octet order
3.3.8 Behavioral descriptions
Figures
Figure 1 \u2013 Example of a confirmed service
Figure 2 \u2013 Memory storage and transmission order for WORD based data types <\/td>\n<\/tr>\n
39<\/td>\nFigure 3 \u2013 Example of a nested state <\/td>\n<\/tr>\n
40<\/td>\n4 Overview of SDCI (IO-LinkTM)
4.1 Purpose of technology
4.2 Positioning within the automation hierarchy
Figure 4 \u2013 SDCI compatibility with IEC 611312
Figure 5 \u2013 Domain of the SDCI technology within the automation hierarchy <\/td>\n<\/tr>\n
41<\/td>\n4.3 Wiring, connectors and power
4.4 Communication features of SDCI <\/td>\n<\/tr>\n
42<\/td>\nFigure 6 \u2013 Generic Device model for SDCI (Master’s view) <\/td>\n<\/tr>\n
43<\/td>\nFigure 7 \u2013 Relationship between nature of data and transmission types <\/td>\n<\/tr>\n
44<\/td>\n4.5 Role of a Master
Figure 8 \u2013 Object transfer at the application layer level (AL) <\/td>\n<\/tr>\n
45<\/td>\n4.6 SDCI configuration
4.7 Mapping to fieldbuses and\/or other upper-level systems
4.8 Standard structure
Figure 9 \u2013 Logical structure of Master and Device <\/td>\n<\/tr>\n
46<\/td>\n5 Physical Layer (PL)
5.1 General
5.1.1 Basics
5.1.2 Topology
Figure 10 \u2013 Three wire connection system <\/td>\n<\/tr>\n
47<\/td>\n5.2 Physical layer services
5.2.1 Overview
Figure 11 \u2013 Topology of SDCI
Figure 12 \u2013 Physical layer (Master) <\/td>\n<\/tr>\n
48<\/td>\n5.2.2 PL services
Figure 13 \u2013 Physical layer (Device)
Tables
Table 1 \u2013 Service assignments of Master and Device
Table 2 \u2013 PL_SetMode <\/td>\n<\/tr>\n
49<\/td>\nTable 3 \u2013 PL_WakeUp
Table 4 \u2013 PL_Transfer <\/td>\n<\/tr>\n
50<\/td>\n5.3 Transmitter\/Receiver
5.3.1 Description method
5.3.2 Electrical requirements
Figure 14 \u2013 Line driver reference schematics
Figure 15 \u2013 Receiver reference schematics <\/td>\n<\/tr>\n
51<\/td>\nFigure 16 \u2013 Reference schematics for SDCI 3-wire connection system
Figure 17 \u2013 Voltage level definitions <\/td>\n<\/tr>\n
52<\/td>\nFigure 18 \u2013 Switching thresholds
Table 5 \u2013 Electrical characteristics of a receiver <\/td>\n<\/tr>\n
53<\/td>\nFigure 19 \u2013 Inrush current and charge (example)
Table 6 \u2013 Electrical characteristics of a Master Port <\/td>\n<\/tr>\n
54<\/td>\nTable 7 \u2013 Electrical characteristics of a Device <\/td>\n<\/tr>\n
55<\/td>\n5.3.3 Timing requirements
Figure 20 \u2013 Power-on timing for Power 1
Figure 21 \u2013 Format of an SDCI UART frame
Table 8 \u2013 Power-on timing <\/td>\n<\/tr>\n
56<\/td>\nFigure 22 \u2013 Eye diagram for the ‘H’ and ‘L’ detection <\/td>\n<\/tr>\n
57<\/td>\nFigure 23 \u2013 Eye diagram for the correct detection of a UART frame
Table 9 \u2013 Dynamic characteristics of the transmission <\/td>\n<\/tr>\n
59<\/td>\n5.4 Power supply
5.4.1 Power supply options
Figure 24 \u2013 Wake-up request
Table 10 \u2013 Wake-up request characteristics <\/td>\n<\/tr>\n
60<\/td>\n5.4.2 Port Class B
Figure 25 \u2013 Class A and B Port definitions
Table 11 \u2013 Electrical characteristics of a Master Port Class B <\/td>\n<\/tr>\n
61<\/td>\n5.4.3 Power-on requirements
5.5 Medium
5.5.1 Connectors
Table 12 \u2013 Master pin assignments <\/td>\n<\/tr>\n
62<\/td>\n5.5.2 Cable
Figure 26 \u2013 Pin layout front view
Table 13 \u2013 Device pin assignments <\/td>\n<\/tr>\n
63<\/td>\n6 Standard Input and Output (SIO)
Figure 27 \u2013 Reference schematics for effective line capacitance and loop resistance
Table 14 \u2013 Cable characteristics
Table 15 \u2013 Cable conductor assignments <\/td>\n<\/tr>\n
64<\/td>\n7 Data link layer (DL)
7.1 General
Figure 28 \u2013 Structure and services of the data link layer (Master) <\/td>\n<\/tr>\n
65<\/td>\n7.2 Data link layer services
7.2.1 DL-B services
Figure 29 \u2013 Structure and services of the data link layer (Device) <\/td>\n<\/tr>\n
66<\/td>\nTable 16 \u2013 Service assignments within Master and Device
Table 17 \u2013 DL_ReadParam <\/td>\n<\/tr>\n
67<\/td>\nTable 18 \u2013 DL_WriteParam <\/td>\n<\/tr>\n
68<\/td>\nTable 19 \u2013 DL_Read
Table 20 \u2013 DL_Write <\/td>\n<\/tr>\n
69<\/td>\nTable 21 \u2013 DL_ISDUTransport <\/td>\n<\/tr>\n
70<\/td>\nTable 22 \u2013 DL_ISDUAbort
Table 23 \u2013 DL_PDOutputUpdate <\/td>\n<\/tr>\n
71<\/td>\nTable 24 \u2013 DL_PDOutputTransport
Table 25 \u2013 DL_PDInputUpdate <\/td>\n<\/tr>\n
72<\/td>\nTable 26 \u2013 DL_PDInputTransport
Table 27 \u2013 DL_PDCycle <\/td>\n<\/tr>\n
73<\/td>\nTable 28 \u2013 DL_SetMode <\/td>\n<\/tr>\n
74<\/td>\nTable 29 \u2013 DL_Mode
Table 30 \u2013 DL_Event <\/td>\n<\/tr>\n
75<\/td>\nTable 31 \u2013 DL_EventConf
Table 32 \u2013 DL_EventTrigger
Table 33 \u2013 DL_Control <\/td>\n<\/tr>\n
76<\/td>\n7.2.2 DL-A services
Table 34 \u2013 DL-A services within Master and Device <\/td>\n<\/tr>\n
77<\/td>\nTable 35 \u2013 OD <\/td>\n<\/tr>\n
78<\/td>\nTable 36 \u2013 PD <\/td>\n<\/tr>\n
79<\/td>\nTable 37 \u2013 EventFlag
Table 38 \u2013 PDInStatus
Table 39 \u2013 MHInfo <\/td>\n<\/tr>\n
80<\/td>\n7.3 Data link layer protocol
7.3.1 Overview
Table 40 \u2013 ODTrig
Table 41 \u2013 PDTrig <\/td>\n<\/tr>\n
81<\/td>\n7.3.2 DL-mode handler
Figure 30 \u2013 State machines of the data link layer
Figure 31 \u2013 Example of an attempt to establish communication <\/td>\n<\/tr>\n
82<\/td>\nFigure 32 \u2013 Failed attempt to establish communication <\/td>\n<\/tr>\n
83<\/td>\nFigure 33 \u2013 Retry strategy to establish communication
Table 42 \u2013 Wake-up procedure and retry characteristics <\/td>\n<\/tr>\n
84<\/td>\nFigure 34 \u2013 Fallback procedure
Table 43 \u2013 Fallback timing characteristics <\/td>\n<\/tr>\n
85<\/td>\nFigure 35 \u2013 State machine of the Master DL-mode handler
Figure 36 \u2013 Submachine 1 to establish communication <\/td>\n<\/tr>\n
86<\/td>\nTable 44 \u2013 State transition table of the Master DL-mode handler <\/td>\n<\/tr>\n
88<\/td>\nFigure 37 \u2013 State machine of the Device DL-mode handler
Table 45 \u2013 State transition table of the Device DL-mode handler <\/td>\n<\/tr>\n
89<\/td>\n7.3.3 Message handler <\/td>\n<\/tr>\n
90<\/td>\nFigure 38 \u2013 SDCI message sequences <\/td>\n<\/tr>\n
91<\/td>\nFigure 39 \u2013 Overview of M-sequence types <\/td>\n<\/tr>\n
92<\/td>\nFigure 40 \u2013 State machine of the Master message handler <\/td>\n<\/tr>\n
93<\/td>\nFigure 41 \u2013 Submachine “Response 3” of the message handler
Figure 42 \u2013 Submachine “Response 8” of the message handler
Figure 43 \u2013 Submachine “Response 15” of the message handler <\/td>\n<\/tr>\n
94<\/td>\nTable 46 \u2013 State transition table of the Master message handler <\/td>\n<\/tr>\n
96<\/td>\nFigure 44 \u2013 State machine of the Device message handler <\/td>\n<\/tr>\n
97<\/td>\n7.3.4 Process Data handler
Table 47 \u2013 State transition table of the Device message handler <\/td>\n<\/tr>\n
98<\/td>\nFigure 45 \u2013 Interleave mode for the segmented transmission of Process Data
Figure 46 \u2013 State machine of the Master Process Data handler <\/td>\n<\/tr>\n
99<\/td>\nFigure 47 \u2013 State machine of the Device Process Data handler
Table 48 \u2013 State transition table of the Master Process Data handler <\/td>\n<\/tr>\n
100<\/td>\n7.3.5 On-request Data handler
Table 49 \u2013 State transition table of the Device Process Data handler <\/td>\n<\/tr>\n
101<\/td>\nFigure 48 \u2013 State machine of the Master On-request Data handler
Table 50 \u2013 State transition table of the Master On-request Data handler <\/td>\n<\/tr>\n
102<\/td>\nFigure 49 \u2013 State machine of the Device On-request Data handler
Table 51 \u2013 State transition table of the Device On-request Data handler <\/td>\n<\/tr>\n
103<\/td>\n7.3.6 ISDU handler
Figure 50 \u2013 Structure of the ISDU <\/td>\n<\/tr>\n
104<\/td>\nTable 52 \u2013 FlowCTRL definitions <\/td>\n<\/tr>\n
105<\/td>\nFigure 51 \u2013 State machine of the Master ISDU handler
Table 53 \u2013 State transition table of the Master ISDU handler <\/td>\n<\/tr>\n
106<\/td>\nFigure 52 \u2013 State machine of the Device ISDU handler <\/td>\n<\/tr>\n
107<\/td>\n7.3.7 Command handler
Table 54 \u2013 State transition table of the Device ISDU handler <\/td>\n<\/tr>\n
108<\/td>\nFigure 53 \u2013 State machine of the Master command handler
Table 55 \u2013 Control codes
Table 56 \u2013 State transition table of the Master command handler <\/td>\n<\/tr>\n
109<\/td>\nFigure 54 \u2013 State machine of the Device command handler <\/td>\n<\/tr>\n
110<\/td>\n7.3.8 Event handler
Table 57 \u2013 State transition table of the Device command handler
Table 58 \u2013 Event memory <\/td>\n<\/tr>\n
111<\/td>\nFigure 55 \u2013 State machine of the Master Event handler <\/td>\n<\/tr>\n
112<\/td>\nFigure 56 \u2013 State machine of the Device Event handler
Table 59 \u2013 State transition table of the Master Event handler <\/td>\n<\/tr>\n
113<\/td>\n8 Application layer (AL)
8.1 General
Table 60 \u2013 State transition table of the Device Event handler <\/td>\n<\/tr>\n
114<\/td>\n8.2 Application layer services
8.2.1 AL services within Master and Device
Figure 57 \u2013 Structure and services of the application layer (Master)
Figure 58 \u2013 Structure and services of the application layer (Device) <\/td>\n<\/tr>\n
115<\/td>\n8.2.2 AL Services
Table 61 \u2013 AL services within Master and Device
Table 62 \u2013 AL_Read <\/td>\n<\/tr>\n
116<\/td>\nTable 63 \u2013 AL_Write <\/td>\n<\/tr>\n
117<\/td>\nTable 64 \u2013 AL_Abort <\/td>\n<\/tr>\n
118<\/td>\nTable 65 \u2013 AL_GetInput <\/td>\n<\/tr>\n
119<\/td>\nTable 66 \u2013 AL_NewInput
Table 67 \u2013 AL_SetInput
Table 68 \u2013 AL_PDCycle <\/td>\n<\/tr>\n
120<\/td>\nTable 69 \u2013 AL_GetOutput
Table 70 \u2013 AL_NewOutput <\/td>\n<\/tr>\n
121<\/td>\nTable 71 \u2013 AL_SetOutput <\/td>\n<\/tr>\n
122<\/td>\nTable 72 \u2013 AL_Event <\/td>\n<\/tr>\n
123<\/td>\n8.3 Application layer protocol
8.3.1 Overview
8.3.2 On-request Data transfer
Table 73 \u2013 AL_Control <\/td>\n<\/tr>\n
124<\/td>\nFigure 59 \u2013 OD state machine of the Master AL
Table 74 \u2013 States and transitions for the OD state machine of the Master AL <\/td>\n<\/tr>\n
126<\/td>\nFigure 60 \u2013 OD state machine of the Device AL
Table 75 \u2013 States and transitions for the OD state machine of the Device AL <\/td>\n<\/tr>\n
127<\/td>\nFigure 61 \u2013 Sequence diagram for the transmission of On-request Data <\/td>\n<\/tr>\n
128<\/td>\nFigure 62 \u2013 Sequence diagram for On-request Data in case of errors
Figure 63 \u2013 Sequence diagram for On-request Data in case of timeout <\/td>\n<\/tr>\n
129<\/td>\n8.3.3 Event processing
Figure 64 \u2013 Event state machine of the Master AL
Table 76 \u2013 State and transitions of the Event state machine of the Master AL <\/td>\n<\/tr>\n
130<\/td>\nFigure 65 \u2013 Event state machine of the Device AL
Table 77 \u2013 State and transitions of the Event state machine of the Device AL <\/td>\n<\/tr>\n
131<\/td>\nFigure 66 \u2013 Single Event scheduling <\/td>\n<\/tr>\n
132<\/td>\n8.3.4 Process Data cycles
Figure 67 \u2013 Sequence diagram for output Process Data <\/td>\n<\/tr>\n
133<\/td>\n9 System Management (SM)
9.1 General
9.2 System Management of the Master
9.2.1 Overview
Figure 68 \u2013 Sequence diagram for input Process Data <\/td>\n<\/tr>\n
134<\/td>\nFigure 69 \u2013 Structure and services of the Master System Management <\/td>\n<\/tr>\n
135<\/td>\n9.2.2 SM Master services
Figure 70 \u2013 Sequence chart of the use case “Port x setup” <\/td>\n<\/tr>\n
136<\/td>\nTable 78 \u2013 SM services within the Master
Table 79 \u2013 SM_SetPortConfig <\/td>\n<\/tr>\n
137<\/td>\nTable 80 \u2013 Definition of the InspectionLevel (IL)
Table 81 \u2013 Definitions of the Target Modes <\/td>\n<\/tr>\n
138<\/td>\nTable 82 \u2013 SM_GetPortConfig <\/td>\n<\/tr>\n
139<\/td>\nTable 83 \u2013 SM_PortMode <\/td>\n<\/tr>\n
140<\/td>\n9.2.3 SM Master protocol
Table 84 \u2013 SM_Operate <\/td>\n<\/tr>\n
141<\/td>\nFigure 71 \u2013 Main state machine of the Master System Management <\/td>\n<\/tr>\n
142<\/td>\nTable 85 \u2013 State transition table of the Master System Management <\/td>\n<\/tr>\n
143<\/td>\nFigure 72 \u2013 SM Master submachine CheckCompatibility_1 <\/td>\n<\/tr>\n
144<\/td>\nTable 86 \u2013 State transition table of the Master submachine CheckCompatibility_1 <\/td>\n<\/tr>\n
145<\/td>\nFigure 73 \u2013 Activity for state “CheckVxy”
Figure 74 \u2013 Activity for state “CheckCompV10” <\/td>\n<\/tr>\n
146<\/td>\nFigure 75 \u2013 Activity for state “CheckComp”
Figure 76 \u2013 Activity (write parameter) in state “RestartDevice” <\/td>\n<\/tr>\n
147<\/td>\nFigure 77 \u2013 SM Master submachine checkSerNum_3
Table 87 \u2013 State transition table of the Master submachine checkSerNum_3 <\/td>\n<\/tr>\n
148<\/td>\n9.3 System Management of the Device
9.3.1 Overview
Figure 78 \u2013 Activity (check SerialNumber) for state CheckSerNum_31 <\/td>\n<\/tr>\n
149<\/td>\nFigure 79 \u2013 Structure and services of the System Management (Device) <\/td>\n<\/tr>\n
150<\/td>\n9.3.2 SM Device services
Figure 80 \u2013 Sequence chart of the use case “INACTIVE \u2013 SIO \u2013 SDCI \u2013 SIO” <\/td>\n<\/tr>\n
151<\/td>\nTable 88 \u2013 SM services within the Device
Table 89 \u2013 SM_SetDeviceCom <\/td>\n<\/tr>\n
152<\/td>\nTable 90 \u2013 SM_GetDeviceCom <\/td>\n<\/tr>\n
153<\/td>\nTable 91 \u2013 SM_SetDeviceIdent <\/td>\n<\/tr>\n
154<\/td>\nTable 92 \u2013 SM_GetDeviceIdent <\/td>\n<\/tr>\n
155<\/td>\nTable 93 \u2013 SM_SetDeviceMode
Table 94 \u2013 SM_DeviceMode <\/td>\n<\/tr>\n
156<\/td>\n9.3.3 SM Device protocol <\/td>\n<\/tr>\n
157<\/td>\nFigure 81 \u2013 State machine of the Device System Management <\/td>\n<\/tr>\n
158<\/td>\nTable 95 \u2013 State transition table of the Device System Management <\/td>\n<\/tr>\n
160<\/td>\nFigure 82 \u2013 Sequence chart of a regular Device startup <\/td>\n<\/tr>\n
161<\/td>\nFigure 83 \u2013 Sequence chart of a Device startup in compatibility mode <\/td>\n<\/tr>\n
162<\/td>\nFigure 84 \u2013 Sequence chart of a Device startup when compatibility fails <\/td>\n<\/tr>\n
163<\/td>\n10 Device
10.1 Overview
Figure 85 \u2013 Structure and services of a Device <\/td>\n<\/tr>\n
164<\/td>\n10.2 Process Data Exchange (PDE)
10.3 Parameter Manager (PM)
10.3.1 General
10.3.2 Parameter Manager state machine <\/td>\n<\/tr>\n
165<\/td>\nFigure 86 \u2013 Parameter Manager (PM) state machine
Table 96 \u2013 State transition table of the PM state machine <\/td>\n<\/tr>\n
167<\/td>\n10.3.3 Dynamic parameter
10.3.4 Single parameter
Figure 87 \u2013 Positive and negative parameter checking result <\/td>\n<\/tr>\n
168<\/td>\n10.3.5 Block Parameter
Table 97 \u2013 Sequence of parameter checks <\/td>\n<\/tr>\n
169<\/td>\nFigure 88 \u2013 Positive Block Parameter download with Data Storage request <\/td>\n<\/tr>\n
170<\/td>\nFigure 89 \u2013 Negative Block Parameter download
Table 98 \u2013 Steps and rules for Block Parameter checking <\/td>\n<\/tr>\n
171<\/td>\n10.3.6 Concurrent parameterization access
10.3.7 Command handling
Table 99 \u2013 Prioritized ISDU responses on command parameters <\/td>\n<\/tr>\n
172<\/td>\n10.4 Data Storage (DS)
10.4.1 General
10.4.2 Data Storage state machine
Figure 90 \u2013 Data Storage (DS) state machine <\/td>\n<\/tr>\n
173<\/td>\nTable 100 \u2013 State transition table of the Data Storage state machine <\/td>\n<\/tr>\n
174<\/td>\n10.4.3 DS configuration
10.4.4 DS memory space
10.4.5 DS Index_List
Figure 91 \u2013 Data Storage request message sequence <\/td>\n<\/tr>\n
175<\/td>\n10.4.6 DS parameter availability
10.4.7 DS without ISDU
10.4.8 DS parameter change indication
10.5 Event Dispatcher (ED)
10.6 Device features
10.6.1 General
10.6.2 Device backward compatibility <\/td>\n<\/tr>\n
176<\/td>\n10.6.3 Protocol revision compatibility
10.6.4 Visual SDCI indication
10.6.5 Parameter access locking
10.6.6 Data Storage locking
10.6.7 Locking of local parameter entries
10.6.8 Locking of local user interface
10.6.9 Offset time <\/td>\n<\/tr>\n
177<\/td>\n10.6.10 Data Storage concept
10.6.11 Block Parameter
10.7 Device reset options
10.7.1 Overview
Figure 92 \u2013 Cycle timing <\/td>\n<\/tr>\n
178<\/td>\n10.7.2 Device reset
10.7.3 Application reset
Table 101 \u2013 Overview on reset options and their impact on Devices <\/td>\n<\/tr>\n
179<\/td>\n10.7.4 Restore factory settings
10.7.5 Back-to-box
10.8 Device design rules and constraints
10.8.1 General
10.8.2 Process Data <\/td>\n<\/tr>\n
180<\/td>\n10.8.3 Communication loss
10.8.4 Direct Parameter
10.8.5 ISDU communication channel
10.8.6 DeviceID rules related to Device variants <\/td>\n<\/tr>\n
181<\/td>\n10.8.7 Protocol constants
10.9 IO Device description (IODD)
10.10 Device diagnosis
10.10.1 Concepts
Table 102 \u2013 Overview of the protocol constants for Devices <\/td>\n<\/tr>\n
182<\/td>\n10.10.2 Events
Table 103 \u2013 Classification of Device diagnosis incidents <\/td>\n<\/tr>\n
183<\/td>\n10.10.3 Visual indicators
Figure 93 \u2013 Event flow in case of successive errors <\/td>\n<\/tr>\n
184<\/td>\n10.11 Device connectivity
11 Master
11.1 Overview
11.1.1 Positioning of Master and Gateway Applications
Figure 94 \u2013 Device LED indicator timing
Table 104 \u2013 Timing for LED indicators <\/td>\n<\/tr>\n
185<\/td>\n11.1.2 Structure, applications, and services of a Master
Figure 95 \u2013 Generic relationship of SDCI and automation technology <\/td>\n<\/tr>\n
186<\/td>\n11.1.3 Object view of a Master and its Ports
Figure 96 \u2013 Structure, applications and services of a Master <\/td>\n<\/tr>\n
187<\/td>\n11.2 Services of the Standardized Master Interface (SMI)
11.2.1 Overview
Figure 97 \u2013 Object model of Master and Ports
Figure 98 \u2013 SMI services <\/td>\n<\/tr>\n
188<\/td>\n11.2.2 Structure of SMI service arguments
Table 105 \u2013 SMI services <\/td>\n<\/tr>\n
189<\/td>\n11.2.3 Concurrency and prioritization of SMI services <\/td>\n<\/tr>\n
190<\/td>\n11.2.4 SMI_MasterIdentification
Table 106 \u2013 SMI_MasterIdentification <\/td>\n<\/tr>\n
191<\/td>\n11.2.5 SMI_PortConfiguration
Table 107 \u2013 SMI_PortConfiguration <\/td>\n<\/tr>\n
192<\/td>\n11.2.6 SMI_ReadbackPortConfiguration <\/td>\n<\/tr>\n
193<\/td>\nTable 108 \u2013 SMI_ReadbackPortConfiguration <\/td>\n<\/tr>\n
194<\/td>\n11.2.7 SMI_PortStatus
Table 109 \u2013 SMI_PortStatus <\/td>\n<\/tr>\n
195<\/td>\n11.2.8 SMI_DSToParServ
Table 110 \u2013 SMI_DSToParServ <\/td>\n<\/tr>\n
196<\/td>\n11.2.9 SMI_ParServToDS <\/td>\n<\/tr>\n
197<\/td>\nTable 111 \u2013 SMI_ParServToDS <\/td>\n<\/tr>\n
198<\/td>\n11.2.10 SMI_DeviceWrite
Table 112 \u2013 SMI_DeviceWrite <\/td>\n<\/tr>\n
199<\/td>\n11.2.11 SMI_DeviceRead
Table 113 \u2013 SMI_DeviceRead <\/td>\n<\/tr>\n
200<\/td>\n11.2.12 SMI_ParamWriteBatch <\/td>\n<\/tr>\n
201<\/td>\nTable 114 \u2013 SMI_ParamWriteBatch <\/td>\n<\/tr>\n
202<\/td>\n11.2.13 SMI_ParamReadBatch
Table 115 \u2013 SMI_ParamReadBatch <\/td>\n<\/tr>\n
203<\/td>\n11.2.14 SMI_PortPowerOffOn <\/td>\n<\/tr>\n
204<\/td>\nTable 116 \u2013 SMI_PortPowerOffOn <\/td>\n<\/tr>\n
205<\/td>\n11.2.15 SMI_DeviceEvent
Table 117 \u2013 SMI_DeviceEvent <\/td>\n<\/tr>\n
206<\/td>\n11.2.16 SMI_PortEvent
11.2.17 SMI_PDIn
Table 118 \u2013 SMI_PortEvent <\/td>\n<\/tr>\n
207<\/td>\nTable 119 \u2013 SMI_PDIn <\/td>\n<\/tr>\n
208<\/td>\n11.2.18 SMI_PDOut
Table 120 \u2013 SMI_PDOut <\/td>\n<\/tr>\n
209<\/td>\n11.2.19 SMI_PDInOut
Table 121 \u2013 SMI_PDInOut <\/td>\n<\/tr>\n
210<\/td>\n11.2.20 SMI_PDInIQ <\/td>\n<\/tr>\n
211<\/td>\nTable 122 \u2013 SMI_PDInIQ <\/td>\n<\/tr>\n
212<\/td>\n11.2.21 SMI_PDOutIQ
Table 123 \u2013 SMI_PDOutIQ <\/td>\n<\/tr>\n
213<\/td>\n11.2.22 SMI_PDReadbackOutIQ
Table 124 \u2013 SMI_PDReadbackOutIQ <\/td>\n<\/tr>\n
214<\/td>\n11.3 Configuration Manager (CM)
11.3.1 Coordination of Master applications <\/td>\n<\/tr>\n
215<\/td>\nFigure 99 \u2013 Coordination of Master applications
Table 125 \u2013 Internal variables and Events controlling Master applications <\/td>\n<\/tr>\n
217<\/td>\n11.3.2 State machine of the Configuration Manager
Figure 100 \u2013 Sequence diagram of start-up via Configuration Manager <\/td>\n<\/tr>\n
218<\/td>\nFigure 101 \u2013 State machine of the Configuration Manager
Table 126 \u2013 State transition table of the Configuration Manager <\/td>\n<\/tr>\n
221<\/td>\nFigure 102 \u2013 Activity for state “CheckPortMode_0” <\/td>\n<\/tr>\n
222<\/td>\n11.4 Data Storage (DS)
11.4.1 Overview
11.4.2 DS data object
11.4.3 Backup and Restore
11.4.4 DS state machine <\/td>\n<\/tr>\n
223<\/td>\nFigure 103 \u2013 Main state machine of the Data Storage mechanism <\/td>\n<\/tr>\n
224<\/td>\nFigure 104 \u2013 Submachine “UpDownload_2” of the Data Storage mechanism <\/td>\n<\/tr>\n
225<\/td>\nFigure 105 \u2013 Data Storage submachine “Upload_7”
Figure 106 \u2013 Data Storage upload sequence diagram <\/td>\n<\/tr>\n
226<\/td>\nFigure 107 \u2013 Data Storage submachine “Download_10”
Figure 108 \u2013 Data Storage download sequence diagram <\/td>\n<\/tr>\n
227<\/td>\nTable 127 \u2013 States and transitions of the Data Storage state machines <\/td>\n<\/tr>\n
229<\/td>\n11.4.5 Parameter selection for Data Storage
11.5 On-request Data exchange (ODE) <\/td>\n<\/tr>\n
230<\/td>\n11.6 Diagnosis Unit (DU)
11.6.1 General
Figure 109 \u2013 State machine of the On-request Data Exchange
Table 128 \u2013 State transition table of the ODE state machine <\/td>\n<\/tr>\n
231<\/td>\n11.6.2 Device specific Events
11.6.3 Port specific Events
Figure 110 \u2013 DeviceEvent flow control
Figure 111 \u2013 Port Event flow control <\/td>\n<\/tr>\n
232<\/td>\n11.6.4 Dynamic diagnosis status
11.6.5 Best practice recommendations
Figure 112 \u2013 SDCI diagnosis information propagation via Events <\/td>\n<\/tr>\n
233<\/td>\n11.7 PD Exchange (PDE)
11.7.1 General
11.7.2 Process Data input mapping
Figure 113 \u2013 Principles of Process Data Input mapping <\/td>\n<\/tr>\n
234<\/td>\n11.7.3 Process Data output mapping
Figure 114 \u2013 Port Qualifier Information (PQI) <\/td>\n<\/tr>\n
235<\/td>\n11.7.4 Process Data invalid\/valid qualifier status
Figure 115 \u2013 Principles of Process Data Output mapping <\/td>\n<\/tr>\n
236<\/td>\n12 Holistic view on Data Storage
12.1 User point of view
Figure 116 \u2013 Propagation of PD qualifier status between Master and Device <\/td>\n<\/tr>\n
237<\/td>\n12.2 Operations and preconditions
12.2.1 Purpose and objectives
12.2.2 Preconditions for the activation of the Data Storage mechanism
12.2.3 Preconditions for the types of Devices to be replaced
12.2.4 Preconditions for the parameter sets <\/td>\n<\/tr>\n
238<\/td>\n12.3 Commissioning
12.3.1 On-line commissioning
12.3.2 Off-site commissioning
Figure 117 \u2013 Active and backup parameter
Figure 118 \u2013 Off-site commissioning <\/td>\n<\/tr>\n
239<\/td>\n12.4 Backup Levels
12.4.1 Purpose
12.4.2 Overview
Table 129 \u2013 Recommended Data Storage Backup Levels <\/td>\n<\/tr>\n
240<\/td>\n12.4.3 Commissioning (“Disable”)
12.4.4 Production (“Backup\/Restore”)
Table 130 \u2013 Criteria for backing up parameters (“Backup\/Restore”) <\/td>\n<\/tr>\n
241<\/td>\n12.4.5 Production (“Restore”)
12.5 Use cases
12.5.1 Device replacement (“Backup\/Restore”)
12.5.2 Device replacement (“Restore”)
12.5.3 Master replacement
Table 131 \u2013 Criteria for backing up parameters (“Restore”) <\/td>\n<\/tr>\n
242<\/td>\n12.5.4 Project replication
13 Integration
13.1 Generic Master model for system integration <\/td>\n<\/tr>\n
243<\/td>\n13.2 Role of gateway applications
13.2.1 Clients
13.2.2 Coordination
13.3 Security
13.4 Special gateway applications
13.4.1 Changing Device configuration including Data Storage
Figure 119 \u2013 Generic Master model for system integration <\/td>\n<\/tr>\n
244<\/td>\n13.4.2 Parameter server and recipe control
13.5 Port and Device Configuration Tool (PDCT)
13.5.1 Strategy
13.5.2 Accessing Masters via SMI
13.5.3 Basic layout examples
Figure 120 \u2013 PDCT via gateway application <\/td>\n<\/tr>\n
245<\/td>\nFigure 121 \u2013 Example 1 of a PDCT display layout
Figure 122 \u2013 Example 2 of a PDCT display layout <\/td>\n<\/tr>\n
246<\/td>\nAnnex A (normative)Codings, timing constraints, and errors
A.1 General structure and encoding of M-sequences
A.1.1 Overview
A.1.2 M-sequence control (MC)
Figure A.1 \u2013 M-sequence control
Table A.1 \u2013 Values of communication channel <\/td>\n<\/tr>\n
247<\/td>\nA.1.3 Checksum\/M-sequence type (CKT)
A.1.4 User data (PD or OD)
Figure A.2 \u2013 Checksum\/M-sequence type octet
Table A.2 \u2013 Values of R\/W
Table A.3 \u2013 Values of M-sequence types <\/td>\n<\/tr>\n
248<\/td>\nA.1.5 Checksum\/status (CKS)
Figure A.3 \u2013 Checksum\/status octet
Table A.4 \u2013 Data types for user data
Table A.5 \u2013 Values of PD status <\/td>\n<\/tr>\n
249<\/td>\nA.1.6 Calculation of the checksum
Figure A.4 \u2013 Principle of the checksum calculation and compression
Table A.6 \u2013 Values of the Event flag <\/td>\n<\/tr>\n
250<\/td>\nA.2 M-sequence types
A.2.1 Overview
A.2.2 M-sequence TYPE_0
A.2.3 M-sequence TYPE_1_x
Figure A.5 \u2013 M-sequence TYPE_0
Figure A.6 \u2013 M-sequence TYPE_1_1 <\/td>\n<\/tr>\n
251<\/td>\nFigure A.7 \u2013 M-sequence TYPE_1_2
Figure A.8 \u2013 M-sequence TYPE_1_V <\/td>\n<\/tr>\n
252<\/td>\nA.2.4 M-sequence TYPE_2_x
Figure A.9 \u2013 M-sequence TYPE_2_1
Figure A.10 \u2013 M-sequence TYPE_2_2 <\/td>\n<\/tr>\n
253<\/td>\nFigure A.11 \u2013 M-sequence TYPE_2_3
Figure A.12 \u2013 M-sequence TYPE_2_4
Figure A.13 \u2013 M-sequence TYPE_2_5 <\/td>\n<\/tr>\n
254<\/td>\nA.2.5 M-sequence type 3
A.2.6 M-sequence type usage for STARTUP, PREOPERATE and OPERATE modes
Figure A.14 \u2013 M-sequence TYPE_2_V
Table A.7 \u2013 M-sequence types for the STARTUP mode
Table A.8 \u2013 M-sequence types for the PREOPERATE mode <\/td>\n<\/tr>\n
255<\/td>\nTable A.9 \u2013 M-sequence types for the OPERATE mode (legacy protocol)
Table A.10 \u2013 M-sequence types for the OPERATE mode <\/td>\n<\/tr>\n
256<\/td>\nA.3 Timing constraints
A.3.1 General
A.3.2 Bit time
A.3.3 UART frame transmission delay of Master (Ports)
A.3.4 UART frame transmission delay of Devices
A.3.5 Response time of Devices
A.3.6 M-sequence time <\/td>\n<\/tr>\n
257<\/td>\nA.3.7 Cycle time
Figure A.15 \u2013 M-sequence timing
Table A.11 \u2013 Recommended MinCycleTimes <\/td>\n<\/tr>\n
258<\/td>\nA.3.8 Idle time
A.3.9 Recovery time
A.4 Errors and remedies
A.4.1 UART errors
A.4.2 Wake-up errors
A.4.3 Transmission errors <\/td>\n<\/tr>\n
259<\/td>\nA.4.4 Protocol errors
A.5 General structure and encoding of ISDUs
A.5.1 Overview
A.5.2 I-Service
Figure A.16 \u2013 I-Service octet <\/td>\n<\/tr>\n
260<\/td>\nA.5.3 Extended length (ExtLength)
Table A.12 \u2013 Definition of the nibble “I-Service”
Table A.13 \u2013 ISDU syntax <\/td>\n<\/tr>\n
261<\/td>\nA.5.4 Index and Subindex
A.5.5 Data
A.5.6 Check ISDU (CHKPDU)
Table A.14 \u2013 Definition of nibble Length and octet ExtLength
Table A.15 \u2013 Use of Index formats <\/td>\n<\/tr>\n
262<\/td>\nA.5.7 ISDU examples
Figure A.17 \u2013 Check of ISDU integrity via CHKPDU
Figure A.18 \u2013 Examples of request formats for ISDUs <\/td>\n<\/tr>\n
263<\/td>\nFigure A.19 \u2013 Examples of response ISDUs <\/td>\n<\/tr>\n
264<\/td>\nA.6 General structure and encoding of Events
A.6.1 General
A.6.2 StatusCode type 1 (no details)
Figure A.20 \u2013 Examples of read and write request ISDUs
Figure A.21 \u2013 Structure of StatusCode type 1 <\/td>\n<\/tr>\n
265<\/td>\nA.6.3 StatusCode type 2 (with details)
Figure A.22 \u2013 Structure of StatusCode type 2
Table A.16 \u2013 Mapping of EventCodes (type 1) <\/td>\n<\/tr>\n
266<\/td>\nA.6.4 EventQualifier
Figure A.23 \u2013 Indication of activated Events
Figure A.24 \u2013 Structure of the EventQualifier
Table A.17 \u2013 Values of INSTANCE <\/td>\n<\/tr>\n
267<\/td>\nA.6.5 EventCode
Table A.18 \u2013 Values of SOURCE
Table A.19 \u2013 Values of TYPE
Table A.20 \u2013 Values of MODE <\/td>\n<\/tr>\n
268<\/td>\nAnnex B (normative)Parameters and commands
B.1 Direct Parameter pages 1 and 2
B.1.1 Overview
Figure B.1 \u2013 Classification and mapping of Direct Parameters <\/td>\n<\/tr>\n
269<\/td>\nB.1.2 MasterCommand
Table B.1 \u2013 Direct Parameter pages 1 and 2 <\/td>\n<\/tr>\n
270<\/td>\nB.1.3 MasterCycleTime and MinCycleTime
Figure B.2 \u2013 MinCycleTime
Table B.2 \u2013 Types of MasterCommands <\/td>\n<\/tr>\n
271<\/td>\nB.1.4 M-sequenceCapability
Figure B.3 \u2013 M-sequenceCapability
Table B.3 \u2013 Possible values of MasterCycleTime and MinCycleTime
Table B.4 \u2013 Values of ISDU <\/td>\n<\/tr>\n
272<\/td>\nB.1.5 RevisionID (RID)
B.1.6 ProcessDataIn
Figure B.4 \u2013 RevisionID
Figure B.5 \u2013 ProcessDataIn <\/td>\n<\/tr>\n
273<\/td>\nB.1.7 ProcessDataOut
B.1.8 VendorID (VID)
B.1.9 DeviceID (DID)
B.1.10 FunctionID (FID)
Table B.5 \u2013 Values of SIO
Table B.6 \u2013 Permitted combinations of BYTE and Length <\/td>\n<\/tr>\n
274<\/td>\nB.1.11 SystemCommand
B.1.12 Device specific Direct Parameter page 2
B.2 Predefined Device parameters
B.2.1 Overview
Figure B.6 \u2013 Index space for ISDU data objects <\/td>\n<\/tr>\n
275<\/td>\nTable B.7 \u2013 Implementation rules for parameters and commands
Table B.8 \u2013 Index assignment of data objects (Device parameter) <\/td>\n<\/tr>\n
277<\/td>\nB.2.2 SystemCommand
Table B.9 \u2013 Coding of SystemCommand (ISDU) <\/td>\n<\/tr>\n
278<\/td>\nB.2.3 DataStorageIndex
Table B.10 \u2013 DataStorageIndex assignments <\/td>\n<\/tr>\n
279<\/td>\nB.2.4 DeviceAccessLocks
Table B.11 \u2013 Structure of Index_List <\/td>\n<\/tr>\n
280<\/td>\nTable B.12 \u2013 Device locking possibilities <\/td>\n<\/tr>\n
281<\/td>\nB.2.5 ProfileCharacteristic
B.2.6 PDInputDescriptor
B.2.7 PDOutputDescriptor
B.2.8 VendorName
B.2.9 VendorText
B.2.10 ProductName
B.2.11 ProductID
B.2.12 ProductText <\/td>\n<\/tr>\n
282<\/td>\nB.2.13 SerialNumber
B.2.14 HardwareRevision
B.2.15 FirmwareRevision
B.2.16 ApplicationSpecificTag
B.2.17 FunctionTag
B.2.18 LocationTag
B.2.19 ErrorCount
B.2.20 DeviceStatus <\/td>\n<\/tr>\n
283<\/td>\nB.2.21 DetailedDeviceStatus
Table B.13 \u2013 DeviceStatus parameter <\/td>\n<\/tr>\n
284<\/td>\nB.2.22 ProcessDataInput
B.2.23 ProcessDataOutput
B.2.24 OffsetTime
Figure B.7 \u2013 Structure of the OffsetTime
Table B.14 \u2013 DetailedDeviceStatus (Index 0x0025) <\/td>\n<\/tr>\n
285<\/td>\nB.2.25 Profile parameter (reserved)
B.2.26 Preferred Index
B.2.27 Extended Index
B.2.28 Profile specific Index (reserved)
Table B.15 \u2013 Time base coding and values of OffsetTime <\/td>\n<\/tr>\n
286<\/td>\nAnnex C (normative)ErrorTypes (ISDU errors)
C.1 General
C.2 Application related ErrorTypes
C.2.1 Overview
Table C.1 \u2013 ErrorTypes <\/td>\n<\/tr>\n
287<\/td>\nC.2.2 Device application error \u2013 no details
C.2.3 Index not available
C.2.4 Subindex not available
C.2.5 Service temporarily not available
C.2.6 Service temporarily not available \u2013 local control
C.2.7 Service temporarily not available \u2013 device control
C.2.8 Access denied
C.2.9 Parameter value out of range
C.2.10 Parameter value above limit
C.2.11 Parameter value below limit <\/td>\n<\/tr>\n
288<\/td>\nC.2.12 Parameter length overrun
C.2.13 Parameter length underrun
C.2.14 Function not available
C.2.15 Function temporarily unavailable
C.2.16 Invalid parameter set
C.2.17 Inconsistent parameter set
C.2.18 Application not ready
C.2.19 Vendor specific
C.3 Derived ErrorTypes
C.3.1 Overview <\/td>\n<\/tr>\n
289<\/td>\nC.3.2 Master \u2013 Communication error
C.3.3 Master \u2013 ISDU timeout
C.3.4 Device Event \u2013 ISDU error
C.3.5 Device Event \u2013 ISDU illegal service primitive
C.3.6 Master \u2013 ISDU checksum error
C.3.7 Master \u2013 ISDU illegal service primitive
C.3.8 Device Event \u2013 ISDU buffer overflow
Table C.2 \u2013 Derived ErrorTypes <\/td>\n<\/tr>\n
290<\/td>\nC.4 SMI related ErrorTypes
C.4.1 Overview
C.4.2 ArgBlock unknown
C.4.3 Incorrect ArgBlock content type
C.4.4 Device not communicating
C.4.5 Service unknown
C.4.6 Process Data not accessible
C.4.7 Insufficient memory
C.4.8 Incorrect Port number
Table C.3 \u2013 SMI related ErrorTypes <\/td>\n<\/tr>\n
291<\/td>\nC.4.9 Incorrect ArgBlock length
C.4.10 Master busy
C.4.11 Inconsistent DS data
C.4.12 Device or Master error <\/td>\n<\/tr>\n
292<\/td>\nAnnex D (normative)EventCodes (diagnosis information)
D.1 General
D.2 EventCodes for Devices
Table D.1 \u2013 EventCodes for Devices <\/td>\n<\/tr>\n
294<\/td>\nD.3 EventCodes for Ports
Table D.2 \u2013 EventCodes for Ports <\/td>\n<\/tr>\n
296<\/td>\nAnnex E (normative)Coding of ArgBlocks
E.1 General
Figure E.1 \u2013 Assignment of ArgBlock identifiers <\/td>\n<\/tr>\n
297<\/td>\nE.2 MasterIdent
Table E.1 \u2013 ArgBlock types and their ArgBlockIDs <\/td>\n<\/tr>\n
298<\/td>\nE.3 PortConfigList
Table E.2 \u2013 MasterIdent <\/td>\n<\/tr>\n
299<\/td>\nTable E.3 \u2013 PortConfigList <\/td>\n<\/tr>\n
300<\/td>\nE.4 PortStatusList <\/td>\n<\/tr>\n
301<\/td>\nTable E.4 \u2013 PortStatusList <\/td>\n<\/tr>\n
302<\/td>\nE.5 On-request_Data
Table E.5 \u2013 On-request_Data <\/td>\n<\/tr>\n
303<\/td>\nE.6 DS_Data
E.7 DeviceParBatch
Table E.6 \u2013 DS_Data
Table E.7 \u2013 DeviceParBatch <\/td>\n<\/tr>\n
304<\/td>\nE.8 IndexList
E.9 PortPowerOffOn
E.10 PDIn
Table E.8 \u2013 IndexList
Table E.9 \u2013 PortPowerOffOn <\/td>\n<\/tr>\n
305<\/td>\nE.11 PDOut
E.12 PDInOut
Table E.10 \u2013 PDIn
Table E.11 \u2013 PDOut <\/td>\n<\/tr>\n
306<\/td>\nE.13 PDInIQ
E.14 PDOutIQ
Table E.12 \u2013 PDInOut
Table E.13 \u2013 PDInIQ <\/td>\n<\/tr>\n
307<\/td>\nE.15 DeviceEvent
E.16 PortEvent
E.17 VoidBlock
Table E.14 \u2013 PDOutIQ
Table E.15 \u2013 DeviceEvent
Table E.16 \u2013 PortEvent <\/td>\n<\/tr>\n
308<\/td>\nE.18 JobError
Table E.17 \u2013 VoidBlock
Table E.18 \u2013 JobError <\/td>\n<\/tr>\n
309<\/td>\nAnnex F (normative)Data types
F.1 General
F.2 Basic data types
F.2.1 General
F.2.2 BooleanT
F.2.3 UIntegerT
Table F.1 \u2013 BooleanT
Table F.2 \u2013 BooleanT coding <\/td>\n<\/tr>\n
310<\/td>\nF.2.4 IntegerT
Figure F.1 \u2013 Coding example of small UIntegerT
Figure F.2 \u2013 Coding example of large UIntegerT
Table F.3 \u2013 UIntegerT
Table F.4 \u2013 IntegerT <\/td>\n<\/tr>\n
311<\/td>\nTable F.5 \u2013 IntegerT coding (8 octets)
Table F.6 \u2013 IntegerT coding (4 octets)
Table F.7 \u2013 IntegerT coding (2 octets)
Table F.8 \u2013 IntegerT coding (1 octet) <\/td>\n<\/tr>\n
312<\/td>\nF.2.5 Float32T
Figure F.3 \u2013 Coding examples of IntegerT
Table F.9 \u2013 Float32T
Table F.10 \u2013 Coding of Float32T <\/td>\n<\/tr>\n
313<\/td>\nF.2.6 StringT
F.2.7 OctetStringT
Figure F.4 \u2013 Singular access of StringT
Table F.11 \u2013 StringT
Table F.12 \u2013 OctetStringT <\/td>\n<\/tr>\n
314<\/td>\nF.2.8 TimeT
Figure F.5 \u2013 Coding example of OctetStringT
Figure F.6 \u2013 Definition of TimeT
Table F.13 \u2013 TimeT <\/td>\n<\/tr>\n
315<\/td>\nF.2.9 TimeSpanT
Table F.14 \u2013 Coding of TimeT
Table F.15 \u2013 TimeSpanT
Table F.16 \u2013 Coding of TimeSpanT <\/td>\n<\/tr>\n
316<\/td>\nF.3 Composite data types
F.3.1 General
F.3.2 ArrayT
F.3.3 RecordT
Figure F.7 \u2013 Example of an ArrayT data structure
Table F.17 \u2013 Structuring rules for ArrayT
Table F.18 \u2013 Example for the access of an ArrayT <\/td>\n<\/tr>\n
317<\/td>\nTable F.19 \u2013 Structuring rules for RecordT
Table F.20 \u2013 Example 1 for the access of a RecordT
Table F.21 \u2013 Example 2 for the access of a RecordT <\/td>\n<\/tr>\n
318<\/td>\nFigure F.8 \u2013 Example 2 of a RecordT structure
Figure F.9 \u2013 Example 3 of a RecordT structure
Table F.22 \u2013 Example 3 for the access of a RecordT <\/td>\n<\/tr>\n
319<\/td>\nFigure F.10 \u2013 Write requests for Example 3 <\/td>\n<\/tr>\n
320<\/td>\nAnnex G (normative)Structure of the Data Storage data object
Table G.1 \u2013 Structure of the stored DS data object
Table G.2 \u2013 Associated header information for stored DS data objects <\/td>\n<\/tr>\n
321<\/td>\nAnnex H (normative)Master and Device conformity
H.1 Electromagnetic compatibility (EMC) requirements
H.1.1 General
H.1.2 Operating conditions
H.1.3 Performance criteria <\/td>\n<\/tr>\n
322<\/td>\nH.1.4 Required immunity tests
Table H.1 \u2013 EMC test conditions for SDCI
Table H.2 \u2013 EMC test levels <\/td>\n<\/tr>\n
323<\/td>\nH.1.5 Required emission tests
H.1.6 Test configurations for Master <\/td>\n<\/tr>\n
324<\/td>\nFigure H.1 \u2013 Test setup for electrostatic discharge (Master)
Figure H.2 \u2013 Test setup for RF electromagnetic field (Master)
Figure H.3 \u2013 Test setup for fast transients (Master) <\/td>\n<\/tr>\n
325<\/td>\nH.1.7 Test configurations for Devices
Figure H.4 \u2013 Test setup for RF common mode (Master)
Figure H.5 \u2013 Test setup for electrostatic discharges (Device) <\/td>\n<\/tr>\n
326<\/td>\nH.2 Test strategies for conformity
H.2.1 Test of a Device
Figure H.6 \u2013 Test setup for RF electromagnetic field (Device)
Figure H.7 \u2013 Test setup for fast transients (Device)
Figure H.8 \u2013 Test setup for RF common mode (Device) <\/td>\n<\/tr>\n
327<\/td>\nH.2.2 Test of a Master <\/td>\n<\/tr>\n
328<\/td>\nAnnex I (informative)Residual error probabilities
I.1 Residual error probability of the SDCI data integrity mechanism
I.2 Derivation of EMC test conditions
Figure I.1 \u2013 Residual error probability for the SDCI data integrity mechanism <\/td>\n<\/tr>\n
330<\/td>\nAnnex J (informative)Example sequence of an ISDU transmission
Figure J.1 \u2013 Example for ISDU transmissions (1 of 2) <\/td>\n<\/tr>\n
332<\/td>\nAnnex K (informative)Recommended methods for detecting parameter changes
K.1 CRC signature
K.2 Revision counter
Table K.1 \u2013 Proper CRC generator polynomials <\/td>\n<\/tr>\n
333<\/td>\nBibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Programmable controllers – Single-drop digital communication interface for small sensors and actuators (SDCI)<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
BSI<\/b><\/a><\/td>\n2022<\/td>\n336<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":409824,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[385,2641],"product_tag":[],"class_list":{"0":"post-409813","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-25-040-40","7":"product_cat-bsi","9":"first","10":"instock","11":"sold-individually","12":"shipping-taxable","13":"purchasable","14":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/409813","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/409824"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=409813"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=409813"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=409813"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}